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APA075-TQG256ES View Datasheet(PDF) - Actel Corporation

Part NameAPA075-TQG256ES ACTEL
Actel Corporation ACTEL
DescriptionProASICPLUS® Flash Family FPGAs
APA075-TQG256ES Datasheet PDF : 178 Pages
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Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
Actel is the leader in low-power and mixed-signal FPGAs and offers the most comprehensive portfolio of
system and power management solutions. Power Matters. Learn more at
Actel Corporation
2061 Stierlin Court
Mountain View, CA
Phone 650.318.4200
Fax 650.318.4600
Actel Europe Ltd.
River Court, Meadows Business Park
Station Approach, Blackwater
Camberley Surrey GU17 9AB
United Kingdom
Phone +44 (0) 1276 609 300
Fax +44 (0) 1276 607 540
Actel Japan
EXOS Ebisu Building 4F
1-24-14 Ebisu Shibuya-ku
Tokyo 150 Japan
Phone +81.03.3445.7671
Fax +81.03.3445.7668
Actel Hong Kong
Room 2107, China Resources Building
26 Harbour Road
Wanchai, Hong Kong
Phone +852 2185 6460
Fax +852 2185 6488
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Device Family Overview
The ProASICPLUS family of devices, Actel’s second generation family of flash FPGAs, offers enhanced performance over Actel’s ProASIC family. It combines the advantages of ASICs with the benefits of programmable devices through nonvolatile flash technology. This enables engineers to create high-density systems using existing ASIC or FPGA design flows and tools. In addition, the ProASICPLUS family offers a unique clock conditioning circuit based on two on-board phase-locked loops (PLLs). The family offers up to one million system gates, supported with up to 198 kbits of two-port SRAM and up to 712 user I/Os, all providing 50 MHz PCI performance.

Features and Benefits
High Capacity
Commercial and Industrial
• 75,000 to 1 Million System Gates
• 27 K to 198 Kbits of Two-Port SRAM
• 66 to 712 User I/Os
• 300, 000 to 1 Million System Gates
• 72 K to 198 Kbits of Two Port SRAM
• 158 to 712 User I/Os

Reprogrammable Flash Technology
• 0.22 µm 4 LM Flash-Based CMOS Process
• Live At Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• No Configuration Device Required
• Retains Programmed Design during Power-Down/Up Cycles
• Mil/Aero Devices Operate over Full Military Temperature Range

• 3.3 V, 32-Bit PCI, up to 50 MHz (33 MHz over military temperature)
• Two Integrated PLLs
• External System Performance up to 150 MHz

Secure Programming
• The Industry’s Most Effective Security Key (FlashLock®)

Low Power
• Low Impedance Flash Switches
• Segmented Hierarchical Routing Structure
• Small, Efficient, Configurable (Combinatorial or Sequential) Logic Cells

High Performance Routing Hierarchy
• Ultra-Fast Local and Long-Line Network
• High-Speed Very Long-Line Network
• High-Performance, Low Skew, Splittable Global Network
• 100% Routability and Utilization

• Schmitt-Trigger Option on Every Input
• 2.5 V / 3.3 V Support with Individually-Selectable Voltage and Slew Rate
• Bidirectional Global I/Os
• Compliance with PCI Specification Revision 2.2
• Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
• Pin-Compatible Packages across the ProASICPLUS Family

Unique Clock Conditioning Circuitry
• PLL with Flexible Phase, Multiply/Divide, and Delay Capabilities
• Internal and/or External Dynamic PLL Configuration
• Two LVPECL Differential Pairs for Clock or Data Inputs

Standard FPGA and ASIC Design Flow
• Flexibility with Choice of Industry-Standard Front-End Tools
• Efficient Design through Front-End Timing and Gate Optimization

ISP Support
• In-System Programming (ISP) via JTAG Port

• SmartGen Netlist Generation Ensures Optimal Usage of Embedded Memory Blocks
• 24 SRAM and FIFO Configurations with Synchronous and Asynchronous Operation up to 150 MHz (typical)


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