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APA1000-PQ256 View Datasheet(PDF) - Actel Corporation

Part NameAPA1000-PQ256 ACTEL
Actel Corporation ACTEL
DescriptionProASICPLUS® Flash Family FPGAs
APA1000-PQ256 Datasheet PDF : 178 Pages
First Prev 171 172 173 174 175 176 177 178
ProASICPLUS Flash Family FPGAs
Previous version Changes in current version (v5.9)
Advance v0.6
(continued)
The "Calculating Typical Power Dissipation" section was updated.
The "Absolute Maximum Ratings*" section was updated.
The "Programming, Storage, and Operating Limits" section was updated.
The "Nominal Supply Voltages’ section was updated.
The "Recommended Operating Conditions" section was updated.
The "DC Electrical Specifications (VDDP = 2.5 V ±0.2V)" section was updated.
The "DC Electrical Specifications (VDDP = 3.3 V ±0.3 V and VDD = 2.5 V ±0.2 V) Applies to
Military Temperature and MIL-STD-883B Temperature Only" section was updated.
The "Synchronous Write and Read to the Same Location" section was updated.
The "Asynchronous Write and Synchronous Read to the Same Location" section was updated.
The "Asynchronous FIFO Read" section was updated.
The "Pin Description" section has been updated.
The "Recommended Design Practice for VPN/VPP" section is new.
The "100-Pin TQFP" section is new.
The "484-Pin FBGA" section is new.
Advance v0.5
Advance v0.4
The description for the VPN pin has changed.
The "Plastic Device Resources" section has been updated.
Figure 2-9 • ProASICPLUS JTAG Boundary Scan Test Logic Circuit and Figure 2-10 • TAP
Controller State Diagram have been updated.
The "Tristate Buffer Delays" section has been updated.
The "Output Buffer Delays" section has been updated.
The "Input Buffer Delays" section has been updated.
The "Global Input Buffer Delays" section has been updated.
The "456-Pin PBGA" section has been updated.
The "676-Pin FBGA" section has been updated.
Advance v0.3
The "ProASICPLUS Product Profile" section has been changed.
The "Plastic Device Resources" section has been updated.
The "ProASICPLUS I/O Power Supply Voltages" sectionhas been updated.
WDATA has ben changed to DI, and RDATA has been changed to DO to make them consistent
with the signal names found in the Macro Library Guide.
Figure 2-18 • Example SRAM Block Diagrams and Figure 2-19 • Basic FIFO Block Diagrams
have been updated.
The "Design Environment" section and Figure 2-23 • Tristate Buffer Delays have been
updated.
The table in the "Package Thermal Characteristics" section has been updated.
The "Calculating Typical Power Dissipation" section is new.
The "Programming, Storage, and Operating Limits" section is new.
The "Nominal Supply Voltages’ section has been updated.
The "DC Electrical Specifications (VDDP = 2.5 V ±0.2V)" section was updated.
The "DC Electrical Specifications (VDDP = 3.3 V ±0.3 V and VDD = 2.5 V ±0.2 V) Applies to
Military Temperature and MIL-STD-883B Temperature Only" section was updated.
The "Recommended Operating Conditions" section was updated.
The "ProASICPLUS Clock Management System" section was updated.
Figure 2-11 • PLL Block – Top-Level View and Detailed PLL Block Diagram was updated.
Figure 2-10 • TAP Controller State Diagram is new.
Tables 5, 6, and 7 from Advanced v0.3 were removed.
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v5.9
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