APA1000-PQ256 View Datasheet(PDF) - Actel Corporation
Part Name
Description
Manufacturer
APA1000-PQ256 Datasheet PDF : 178 Pages
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ProASICPLUS Flash Family FPGAs
Previous version Changes in current version (v5.9)
v2.0
(continued)
Advance v0.7
The following pins have been changed in the "1152-Pin FBGA" table:
Pin Number
Function
Pin Number
Function
U4
I/O (GLMX1)
U29
NPECL2
U6
NPECL1
U31
I/O (GLMX2)
U7
GL1
V28
PPECL2 (I/P)
V5
GL2
V29
GL4
V6
PPECL1 (I/P)
V30
GL3
The "ProASICPLUS Architecture" section was updated.
The "Array Coordinates" section and Table 2-2 • Array Coordinates are new.
The "Power-Up Sequencing" section is new.
"I/O Features" section was updated.
The "Timing Control and Characteristics" section was updated. "Physical Implementation"
section, "Functional Description" section, "Lock Signal" section, and "PLL Configuration
Options" section are new.
"PLL Block – Top-Level View and Detailed PLL Block Diagram" section was updated.
Figure 2-12 • Input Connectors to ProASICPLUS Clock Conditioning Circuitry was updated.
"Sample Implementations" section, "Adjustable Clock Delay" section, and the "Clock Skew
Minimization" section are new.
Figure 2-13 • Using the PLL 33 MHz In, 133 MHz Outthrough and Figure 2-17 • Using the PLL
for Clock Deskewing are new.
The "PLL Electrical Specifications" section is new.
The "Design Environment" section was updated.
Figure 2-23 • Tristate Buffer Delays was updated.
The "Calculating Typical Power Dissipation" section was updated.
The "DC Electrical Specifications (VDDP = 2.5 V ±0.2V)" section was updated.
The Table 2-24 • DC Electrical Specifications (VDDP = 3.3 V ±0.3 V and VDD = 2.5 V ±0.2 V)
Applies to Military Temperature and MIL-STD-883B Temperature Only was updated.
The "DC Specifications (3.3 V PCI Operation)1" section was updated.
The "Tristate Buffer Delays" section (the figure and table) have been updated.
The "Output Buffer Delays" section (the figure and table) have been updated.
The "Input Buffer Delays" section was updated.
The "Global Input Buffer Delays" section was updated.
The "Predicted Global Routing Delay" section was updated.
The "Global Routing Skew" section was updated.
The "Sample Macrocell Library Listing" section was updated.
The "Pin Description" section was updated. GLMX is new.
The "Recommended Design Practice for VPN/VPP" section was updated.
Advance v0.6
Pin AK31 of FG1152 for the APA1000 changed to VPP.
The "Features and Benefits" section were updated.
The "ProASICPLUS Product Profile" section was updated.
The "Ordering Information" section was updated.
The "Plastic Device Resources" was updated.
The "ProASICPLUS Architecture" section was updated.
Table 2-1 • Clock Spines was updated.
Figure 2-11 • PLL Block – Top-Level View and Detailed PLL Block Diagram was updated.
The "Design Environment" section was updated.
The "Package Thermal Characteristics" section was updated.
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4-6
v5.9
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