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APA1000-TQG144ES View Datasheet(PDF) - Actel Corporation

Part NameAPA1000-TQG144ES ACTEL
Actel Corporation ACTEL
DescriptionProASICPLUS® Flash Family FPGAs
APA1000-TQG144ES Datasheet PDF : 178 Pages
First Prev 171 172 173 174 175 176 177 178
ProASICPLUS Flash Family FPGAs
Previous version Changes in current version (v5.9)
v3.2
The "ProASICPLUS Clock Management System" section was updated.
Figure 2-11 • PLL Block – Top-Level View and Detailed PLL Block Diagram was updated.
Table 2-7 • Clock-Conditioning Circuitry MUX Settings is new.
Figure 2-17 • Using the PLL for Clock Deskewing was updated.
The "PLL Electrical Specifications" section was updated.
Figure 2-23 • Tristate Buffer Delays was updated.
In the "Calculating Typical Power Dissipation" section, P9 was changed to 7.5 mW.
The "Programming, Storage, and Operating Limits" section was updated.
The "Recommended Design Practice for VPN/VPP" section was updated.
v3.1
The datasheet was updated to include references to guidelines concerning the use of certain
ProASICPLUS I/O standards.
v3.0
In Table 2-2 • Array Coordinates, the Memory Rows – Bottom coordinates were changed.
Figure 2-5 • Core Cell Coordinates for the APA1000 was updated.
The VIL Minimum in the Table 2-24 • DC Electrical Specifications (VDDP = 3.3 V ±0.3 V and VDD
= 2.5 V ±0.2 V) Applies to Military Temperature and MIL-STD-883B Temperature Only was
changed from 0.3 to –0.3.
In the "Output Buffer Delays" section, the OB25LPLL tDHL Standard changed to 5.3.
In the "Sample Macrocell Library Listing" section, the AND2 Standard maximum changed to 0.7
and the –F maximum changed to 0.8.
v2.0
The Table 1 • ProASICPLUS Product Profile was updated.
The "Ordering Information" section was updated.
The "Plastic Device Resources" section was updated.
The "ProASICPLUS Architecture" section was updated.
Table 2-2 • Array Coordinates was updated.
Figure 2-5 • Core Cell Coordinates for the APA1000 is new.
Figure 2-8 • LVPECL High and Low Threshold Values is new.
The Introduction section in the "ProASICPLUS Clock Management System" section was updated.
The "Physical Implementation" section was updated.
The "Functional Description" section was updated.
Figure 2-11 • PLL Block – Top-Level View and Detailed PLL Block Diagram through Figure 2-
17 • Using the PLL for Clock Deskewing were updated.
The "PLL Electrical Specifications" section was updated.
Figure 2-22 • Multi-Port Memory Usage was updated.
The "Calculating Typical Power Dissipation" section was updated.
The "Nominal Supply Voltages’ section was updated.
The Table 2-24 • DC Electrical Specifications (VDDP = 3.3 V ±0.3 V and VDD = 2.5 V ±0.2 V)
Applies to Military Temperature and MIL-STD-883B Temperature Only was updated.
The "Tristate Buffer Delays" section was updated.
The "Output Buffer Delays" section was updated.
The"Input Buffer Delays" section was updated.
"Global Routing Skew" section was updated.
The"Sample Macrocell Library Listing" section was updated.
The "Pin Description" section was updated.
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v5.9
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