APA1000-PQ256 View Datasheet(PDF) - Actel Corporation
Part Name
Description
Manufacturer
APA1000-PQ256 Datasheet PDF : 178 Pages
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ProASICPLUS Flash Family FPGAs
Previous version Changes in current version (v5.9)
v4.1
(continued)
Figure 2-27 • JTAG Operation Timing is new.
Note 1 in Table 2-52 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial was
updated.
The notes in Table 2-56 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
were updated.
A note was added to Figure 2-45 • FIFO Reset.
A note was added to Table 2-68 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/
Industrial.
The "TRST Test Reset Input" section was updated in the "Pin Description" section.
The "624-Pin CCGA/LGA" section was updated for the APA600 and APA1000. Please review all
pin data.
v4.0
Figure 2-17 • Using the PLL for Clock Deskewing was updated.
Table 2-48 • Recommended Operating Conditions was updated.
The "1152-Pin FBGA" figure was updated.
Pin names were changed to more accurately reflect the multiple functions supported by each
pin.
v3.5
The ProASICPLUS and ProASICPLUS Military/Aerospace datasheets were combined. This
document now supports Commercial, Industrial, and Military Temperature devices.
Table 1 • ProASICPLUS Product Profile was updated.
The "Ordering Information" section was updated.
"Plastic Device Resources" table was updated.
The Long Term Jitter Peak-to-Peak Max. in the "PLL Electrical Specifications" table was updated.
The "Calculating Typical Power Dissipation" section was updated.
"Performance Retention" section
Table 2-19 • Military Temperature Grade Product Performance Retention
Table 2-21 • Recommended Operating Conditions was updated.
Table 2-22 • DC Electrical Specifications (VDDP = 2.5 V ±0.2V) was updated.
Table 2-24 • DC Electrical Specifications (VDDP = 3.3 V ±0.3 V and VDD = 2.5 V ±0.2 V) Applies
to Military Temperature and MIL-STD-883B Temperature Only was updated.
Table 2-48 • Recommended Operating Conditions was updated.
v3.4
The "Temperature Grade Offerings" table is new.
The "Speed Grade and Temperature Matrix" table is new.
The "ProASICPLUS Clock Management System" section was updated.
The "Lock Signal" section was updated.
The "PLL Electrical Specifications" table was updated.
The "User Security" section was updated.
The "Design Environment" section was updated.
Table 2-16 • Package Thermal Characteristics was updated.
The "Asynchronous FIFO Full and Empty Transitions" section was updated.
The "AVDD PLL Power Supply" section in the "Pin Description" section was updated.
v3.3
The "144-Pin TQFP" table was updated. The following pins changed:
Pin 15 = GLMX1
Pin 16 = GL1
Pin 21 = GL2
Pin 88 = GL3
Pin93 = GL4
Pin 94 = GLMX2
Page
2-53
2-55
2-59
2-72
2-72
2-73
3-78
2-16
2-52
3-69
i
ii
ii
2-18
2-28
2-31
2-32
2-33
2-34
2-38
2-52
iv
iv
2-10
2-13
2-18
2-20
2-25
2-27
2-65
2-73
3-4
v5.9
4-3
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