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APA1000-TQG144ES View Datasheet(PDF) - Actel Corporation

Part NameAPA1000-TQG144ES ACTEL
Actel Corporation ACTEL
DescriptionProASICPLUS® Flash Family FPGAs
APA1000-TQG144ES Datasheet PDF : 178 Pages
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ProASICPLUS Flash Family FPGAs
Input/Output Blocks
To meet complex system demands, the ProASICPLUS
family offers devices with a large number of user I/O
pins; up to 712 on the APA1000. Table 2-3 shows the
available supply voltage configurations (the PLL block
uses an independent 2.5 V supply on the AVDD and
AGND pins). All I/Os include ESD protection circuits. Each
I/O has been tested to 2000 V to the human body model
(per JESD22 (HBM)).
Six or seven standard I/O pads are grouped with a GND
pad and either a VDD (core power) or VDDP (I/O power)
pad. Two reference bias signals circle the chip. One
protects the cascaded output drivers, while the other
creates a virtual VDD supply for the I/O ring.
I/O pads are fully configurable to provide the maximum
flexibility and speed. Each pad can be configured as an
input, an output, a tristate driver, or a bidirectional
buffer (Figure 2-6 and Table 2-4).
Table 2-3 • ProASICPLUS I/O Power Supply Voltages
2.5 V
VDDP
3.3 V
Input Compatibility
2.5 V
3.3 V
Output Drive
2.5 V
3.3 V
3.3 V / 2.5 V
Signal Control
Pull-up
Control
Y
EN
Pad
A
3.3 V / 2.5 V Signal Control Drive
Strength and Slew-Rate Control
Figure 2-6 • I/O Block Schematic Representation
Table 2-4 • I/O Features
Function
Description
I/O pads configured as inputs
• Selectable 2.5 V or 3.3 V threshold levels
• Optional pull-up resistor
• Optionally configurable as Schmitt trigger input. The Schmitt trigger input option can be
configured as an input only, not a bidirectional buffer. This input type may be slower than
a standard input under certain conditions and has a typical hysteresis of 0.35 V. I/O macros
with an "S" in the standard I/O library have added Schmitt capabilities.
• 3.3 V PCI Compliant (except Schmitt trigger inputs)
I/O pads configured as outputs
• Selectable 2.5 V or 3.3 V compliant output signals
• 2.5 V – JEDEC JESD 8-5
• 3.3 V – JEDEC JESD 8-A (LVTTL and LVCMOS)
• 3.3 V PCI compliant
• Ability to drive LVTTL and LVCMOS levels
• Selectable drive strengths
• Selectable slew rates
• Tristate
I/O pads configured as bidirectional • Selectable 2.5 V or 3.3 V compliant output signals
buffers
• 2.5 V – JEDEC JESD 8-5
• 3.3 V – JEDEC JESD 8-A (LVTTL and LVCMOS)
• 3.3 V PCI compliant
• Optional pull-up resistor
• Selectable drive strengths
• Selectable slew rates
• Tristate
2-6
v5.9
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