Integrated circuits, Transistor, Semiconductors Free Datasheet Search and Download Site


APA075-TQG144I View Datasheet(PDF) - Actel Corporation

Part NameAPA075-TQG144I ACTEL
Actel Corporation ACTEL
DescriptionProASICPLUS® Flash Family FPGAs
APA075-TQG144I Datasheet PDF : 178 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
General Description
ProASICPLUS Flash Family FPGAs
Routing Resources
The routing structure of ProASICPLUS devices is designed
to provide high performance through a flexible four-
level hierarchy of routing resources: ultra-fast local
resources, efficient long-line resources, high-speed, very
long-line resources, and high performance global
networks.
The ultra-fast local resources are dedicated lines that
allow the output of each tile to connect directly to every
input of the eight surrounding tiles (Figure 2-1).
The efficient long-line resources provide routing for
longer distances and higher fanout connections. These
resources vary in length (spanning 1, 2, or 4 tiles), run
both vertically and horizontally, and cover the entire
ProASICPLUS device (Figure 2-2 on page 2-2). Each tile can
drive signals onto the efficient long-line resources, which
can in turn access every input of every tile. Active buffers
are inserted automatically by routing software to limit
the loading effects due to distance and fanout.
The high-speed, very long-line resources, which span the
entire device with minimal delay, are used to route very
long or very high fanout nets. (Figure 2-3 on page 2-3).
The high-performance global networks are low-skew,
high fanout nets that are accessible from external pins or
from internal logic (Figure 2-4 on page 2-4). These nets
are typically used to distribute clocks, resets, and other
high fanout nets requiring a minimum skew. The global
networks are implemented as clock trees, and signals can
be introduced at any junction. These can be employed
hierarchically with signals accessing every input on all
tiles.
L
L
L
Inputs
L
L
L
L
L
Ultra-Fast
Local Lines
(connects a tile to the
adjacent tile, I/O buffer,
or memory block)
L
Figure 2-1 • Ultra-Fast Local Resources
v5.9
2-1
Direct download click here
 
HOME 'APA075-TQG144I' Search
Share Link : 
한국어     日本語     русский     简体中文     español
@ 2015 - 2018  [ Home  ] [ Privacy Policy ] [ Request Datasheet  ] [ Contact Us ]