MAX1247ACEE(1997) View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX1247ACEE Datasheet PDF : 24 Pages
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+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
______________________________________________________________Pin Description
PIN
NAME
FUNCTION
1
VDD
Positive Supply Voltage
2–5
CH0–CH3 Sampling Analog Inputs
6
COM
Ground reference for analog inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1246/MAX1247 down; otherwise, they
7
SHDN
are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation
mode. Letting SHDN float puts the reference-buffer amplifier in external compensation mode.
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
8
VREF
In internal reference mode (MAX1246 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
REFADJ to VDD.
9
REFADJ
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD.
10
AGND
Analog Ground
11
DGND
Digital Ground
12
DOUT
Serial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1246/MAX1247 begin the
13
SSTRB
A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses
high for one clock period before the MSB decision. High impedance when CS is high (external clock
mode).
14
DIN
Serial Data Input. Data is clocked in at SCLK’s rising edge.
15
CS
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
16
SCLK
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)
VDD
DOUT
6k
DOUT
6k
DGND
CLOAD
50pF
CLOAD
50pF
DGND
a) High-Z to VOH and VOL to VOH
b) High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for Enable Time
DOUT
6k
DGND
VDD
6k
DOUT
CLOAD
50pF
CLOAD
50pF
DGND
a) VOH to High-Z
b) VOL to High-Z
Figure 2. Load Circuits for Disable Time
8 _______________________________________________________________________________________
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