MAX1247AEPE(1997) View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX1247AEPE
(Rev.:1997)

+2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16

Maxim Integrated 

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

CS

SSTRB

•••

tSDV

•••

•••

tSTR

•••

tSSTRB

tSSTRB

SCLK

••••

• • ••

PD0 CLOCKED IN

Figure 7. External Clock Mode SSTRB Detailed Timing

CS

SCLK

1 2 345678

9 10 11 12

DIN

SSTRB

DOUT

SEL2 SEL1 SEL0

UNI/

BIP

SGL/

DIF

PD1

PD0

START

tCONV

A/D STATE

ACQUISITION CONVERSION

IDLE

1.5µs

7.5µs MAX

(fSCLK = 2MHz) (SHDN = FLOAT)

B11

MSB

B10

B9

IDLE

Figure 8. Internal Clock Mode Timing

18 19 20 21 22 23 24

B2

B1

B0 FILLED WITH

LSB ZEROS

conversion already in progress. When internal clock

mode is selected, SSTRB does not go into a high-

impedance state when CS goes high.

Figure 9 shows the SSTRB timing in internal clock

mode. In this mode, data can be shifted in and out of

the MAX1246/MAX1247 at clock rates exceeding

2.0MHz if the minimum acquisition time (tACQ) is kept

above 1.5µs.

Data Framing

The falling edge of CS does not start a conversion.

The first logic high clocked into DIN is interpreted as a

start bit and defines the first bit of the control byte. A

conversion starts on SCLK’s falling edge, after the eighth

bit of the control byte (the PD0 bit) is clocked into DIN.

The start bit is defined as follows:

The first high bit clocked into DIN with CS low any

time the converter is idle; e.g., after VDD is applied.

OR

The first high bit clocked into DIN after bit 5 of a con-

version in progress is clocked onto the DOUT pin.

If CS is toggled before the current conversion is com-

plete, the next high bit clocked into DIN is recognized as

a start bit; the current conversion is terminated, and a

new one is started.

______________________________________________________________________________________ 13

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