Parameter
High level output voltage
Low level output voltage
Symbol
VOH
VOL
Minimum
3.0
-
7.2 AC Timing Characteristics
7.2.1 Cold Reset
Parameter
RESET# active low pulse width
RESET# inactive to BIT_CLK
Startup delay
Symbol
Trst_low
Trst2clk
Minimum
1.0
162.8
Typical
3.3
0
Typical
-
-
ALC250 Data Sheet
Maximum
Units
V
0.5
V
Maximum
-
-
Units
µs
ns
7.2.2 Warm Reset
Parameter
SYNC active high pulse width
SYNC inactive to BIT_CLK
Startup delay
Cold reset timing diagram
Symbol
Tsync_high
Tsync2clk
Minimum
1.0
162.8
Typical
-
-
Maximum
-
-
Units
µs
ns
Warm reset timing diagram
7.2.3 AC-Link Clocks
Parameter
Symbol
BIT_CLK frequency
BIT_CLK period
BIT_CLK output jitter
Tclk_period
BIT_CLK high pulse width (note 2)
Tclk_high
BIT_CLK low pulse width (note 2)
SYNC frequency
Tclk_low
SYNC period
SYNC high pulse width
Tsync_period
Tsync_high
SYNC low pulse width
Tsync_low
Note 1: Worse case duty cycle restricted to 45/55.
Minimum
-
-
-
36
36
-
-
-
-
Typical
12.288
81.4
-
40.7
40.7
48.0
20.8
1.3
19.5
Maximum
-
-
750
45
45
-
-
-
-
Units
MHz
ns
ps
ns
ns
KHz
µs
µs
µs
Two Channel AC’97 2.3 Audio Codec
29
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