ALC250 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

ALC250

TWO CHANNEL AC’97 2.3 AUDIO CODEC with EQUALIZER

Unspecified 

6.2 Vendor Defined Registers (Page ID-00h)

These registers are available to Realtek and Realtek customers for specialized functions.

6.2.1 MX60 S/PDIF Input Channel Status [15:0]

Default: 0000h

The data in MX60 are captured from channel status [15:0] of S/PDIF-IN signal.

Bit Type

Function

15

R LEVEL (Generation Level)

14:8

R CC[6:0] (Category Code)

7:6

R Mode[1:0]

5:3

R PRE[2:0] (Pre-Emphasis)

2

R COPY (Copyright)

0: asserted 1: Not asserted

1

R /AUDIO (Non-Audio Data type)

0: PCM data 1: AC3 or other digital non-audio data

0

R PRO (Professional or Consumer format)

0: consumer format 1: professional format

ALC250 Data Sheet

6.2.2 MX62 S/PDIF Input Channel Status [29:15]

Default: 0000h

The data in MX62 are captured from channel status [29:16] of S/PDIF-IN signal.

Bit

15

14

13:12

11:8

7:4

3:0

Type

R

R

R

R

R

R

Function

“V” bit in sub-frame of SPDIFI

0: Data X and Y are valid

1: At least one of data X and Y is invalid

This bit is real-time updated, and it is meaning when S/PDIF-IN is locked

S/PDIF-IN Input Signal Locked by hardware

0: Unlocked 1: Locked

Ca[1:0] ( Clock Accuracy)

Fs[3:0]. (Sample Frequency in channel status)

0000: 44.1KHz

0010: 48 KHz

0011: 32 KHz

Others: Reserved

Cn[3:0] (Channel Number)

Sn[3:0] (Source Number)

6.2.3 MX64 EQualizer Control Index Port

Default: 0000h

Bit Type

Function

15:6 NA Reserved

3:0

R/W EQ Control Registers Index

6.2.4 MX64 EQualizer Control Data Port

Default: 0000h

Bit Type

Function

15:0 R/W EQ Control Registers Data

Two Channel AC’97 2.3 Audio Codec

18

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