ALC250 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

ALC250

TWO CHANNEL AC’97 2.3 AUDIO CODEC with EQUALIZER

Unspecified 

ALC250 Data Sheet

6.1.16 MX22 3D Control

Default: 0000h

This register is used to control the 3D stereo enhancement function built into the AC’97 component. The register bits, DP2-DP0

are used to control the separation ratios in the analog 3D and digital 3D for both LINE_OUT and HP_OUT.

The 3D stereo function provides for a deeper and wider sound experience. Note that the 3D bit in the MX20.[13] must be set to

1 to enable this function.

Bit Type

15:3

Reserved, Read as 0

2:0

R/W Depth Control (DP[2:0])

3D effect control

DP[2:0] Function DP[2:0]

000

0% (off)

100

001

12.5%

101

010

25%

110

011

37.5

111

Function

Function

50%

67.5%

75%

100%

6.1.17 MX24 Audio interrupt and Paging

Default: 0000h

Bit Type

Function

15

Interrupt Status, I4

0: Interrupt is clear.

1: Interrupt was generated

Interrupt event and status are clear by writing a 1 to this bit. The status will change regardless of interrupt

enable (I0).

14

R Interrupt Cause, I3

I3=0: GPIO, SPDIF-IN and Jack-Detect interrupt status in MX78 are not changed.

1: GPIO, SPDIF-IN and Jack-Detect interrupt status in MX78 are changed.

I3= (MX78.14|MX78.13|MX78.12|MX78.6|MX78.5|MX78.4)

This bit reflects the cause of the first interrupt event generated. Software should read it after interrupt

status (I4) has been confirmed as interrupting. I3 will be zero when I4 is cleared.

13

R Interrupt Cause, I2

I2=0: Sense value in page ID-01h MX6A.[12:8] has not changed.

1: Sense cycle completed or new sense value in page ID-01h MX6A.[12:8] is available.

This bit reflects the cause of the first interrupt event generated. Software should read it after interrupt

status (I4) has been confirmed as interrupting. I2 will be zero when I4 is cleared.

12

R/W Sense Cycle, I1

0: Sense cycle not in progress

1: Sense cycle start

Writing a ‘1’ to this bit causes a sense cycle start. If a sense cycle is in progress, writing a ‘0’ to this bit will

abort the sense cycle.

Whether the data in the sense result register (page ID-01h MX6A) is valid or not is determined by the IV

bit in MX6A, Page ID-1h.

11

R/W Interrupt Enable, I0

0: Interrupt is masked, interrupt status (I4) will not be shown in bit 0 in Slot 12 in SDATA-IN.

1: Interrupt is un-masked, interrupt status (I4) will be shown in bit 0 in Slot 12 in SDATA-IN.

10:4 NA Reserved, read as 0

3:0

R/W Page Selector, PG[3:0]

0000b: Vendor Specific

0001b: Page ID 01 (AC’97 2.3 Discovery Descriptor Definition)

Others: Reserved.

This register is used to select a descriptor of 16 word pages between registers MX60 to MX6F. Value of 0

is used to select vendor specific space to maintain compatibility with AC’97 2.2 vendor specific register.

Two Channel AC’97 2.3 Audio Codec

13

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Rev1.01

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