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ADV7441ABSTZ-5P1 View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADV7441ABSTZ-5P1 Datasheet PDF : 28 Pages
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ADV7441A
TIMING CHARACTERISTICS
AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V,
CVDD = 1.71 V to 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted.
Table 4.
Parameter1, 2
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
Crystal Frequency Stability
Horizontal Sync Input Frequency
LLC Frequency Range
I2C PORTS (FAST MODE)3
xCL Frequency4
xCL Minimum Pulse Width High4
xCL Minimum Pulse Width Low4
Hold Time (Start Condition)
Setup Time (Start Condition)
xDA Setup Time4
xCL and xDA Rise Times4
xCL and xDA Fall Times4
Setup Time for Stop Condition
I2C PORTS (NORMAL MODE)3
xCL Frequency4
xCL Minimum Pulse Width High4
xCL Minimum Pulse Width Low4
Hold Time (Start Condition)
Setup Time (Start Condition)
xDA Setup Time4
xCL and xDA Rise Times4
xCL and xDA Fall Times4
Setup Time for Stop Condition
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC Mark Space Ratio
DATA AND CONTROL OUTPUTS
Data Output Transition Time SDR (SDP)5
Data Output Transition Time SDR (CP)6
I2S PORT (MASTER MODE)
SCLK Mark Space Ratio
LRCLK Data Transition Time
I2Sx Data Transition Time7
MCLKOUT Frequency
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t1
t2
t3
t4
t5
t6
t7
t8
t9:t10
t11
t12
t13
t14
t15:t16
t17
t18
t19
t20
Test Conditions
Negative clock edge to start of valid data
End of valid data to negative clock edge
End of valid data to negative clock edge
Negative clock edge to start of valid data
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
Min
14.8
12.825
0.6
1.3
0.6
0.6
100
0.6
4
4.7
4
4.7
250
4
5
45:55
45:55
4.096
Typ
28.6363
Max
±50
110
170
400
300
300
100
1000
300
55:45
3.4
2.4
2
0.5
55:45
10
10
5
5
24.576
Unit
MHz
ppm
kHz
MHz
kHz
μs
μs
μs
μs
ns
ns
ns
μs
kHz
μs
μs
μs
μs
ns
ns
ns
μs
ms
% duty cycle
ns
ns
ns
ns
% duty cycle
ns
ns
ns
ns
MHz
1 The minimum/maximum specifications are guaranteed over the −40°C to +85°C temperature range (TMIN to TMAX).
2 Guaranteed by characterization.
3 Refers to all I2C pins (DDC and control port).
4 The prefix x refers to pin names beginning with S, DDCA_S, and DDCB_S.
5 SDP timing figures were obtained using the default drive strength value (0x15) in User Map Register 0xF4.
6 CP timing figures were obtained using the maximum drive strength value (0x3F) in User Map Register 0xF4.
7 The suffix x refers to pin names ending with 0, 1, 2, and 3.
Rev. B | Page 8 of 28
 

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