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ADV7393BCPZ-REEL View Datasheet(PDF) - Analog Devices

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Description
Manufacturer
ADV7393BCPZ-REEL Datasheet PDF : 108 Pages
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Data Sheet
ADV7390/ADV7391/ADV7392/ADV7393
SPECIFICATIONS
POWER SUPPLY SPECIFICATIONS
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 3.
Parameter
Min
SUPPLY VOLTAGES
VDD
1.71
VDD_IO
1.71
PVDD
1.71
VAA
2.6
POWER SUPPLY REJECTION RATIO
Typ
Max
Unit
1.8
1.89
V
3.3
3.63
V
1.8
1.89
V
3.3
3.465
V
0.002
%/%
INPUT CLOCK SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 4.
Parameter
fCLKIN
CLKIN High Time, t9
CLKIN Low Time, t10
CLKIN Peak-to-Peak Jitter Tolerance
Conditions1
SD/ED
ED (at 54 MHz)
HD
Min
Typ
Max
27
54
74.25
40
40
2
1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition.
Unit
MHz
MHz
MHz
% of one clock cycle
% of one clock cycle
±ns
ANALOG OUTPUT SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 5.
Parameter
Full-Drive Output Current
Low-Drive Output Current
DAC-to-DAC Matching
Output Compliance, VOC
Output Capacitance, COUT
Analog Output Delay2
DAC Analog Output Skew
Conditions
RSET = 510 Ω, RL = 37.5 Ω
All DACs enabled
RSET = 510 Ω, RL = 37.5 Ω
DAC 1 enabled only1
RSET = 4.12 kΩ, RL = 300 Ω
DAC 1, DAC 2, DAC 3
DAC 1, DAC 2, DAC 3
Min
Typ
Max
Unit
33
34.6
37
mA
31.5
33.5
37
mA
4.3
mA
2.0
%
0
1.4
V
10
pF
6
ns
1
ns
1 The recommended method of bringing this value back to the ideal value is by adjusting Register 0x0B to the recommended value of 0x12.
2 Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition.
Rev. G | Page 7 of 108
 

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