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ADV7181DBCPZ View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADV7181DBCPZ Datasheet PDF : 24 Pages
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Data Sheet
ADV7181D
Pin No.
33
34 to 38, 45 to 49
39, 40
Mnemonic
SOG
AIN1 to AIN10
CAPY1, CAPY2
Type
Input
Input
Input
41
AVDD
Power
42
REFOUT
Output
43
CML
Output
44
CAPC2
Input
50
SOY
Input
51
RESET
Input
52
ALSB
Input
53
SDATA
Input/
Output
54
SCLK
Input
55
VS_IN
Input
56
HS_IN/CS_IN Input
63
FIELD/DE
Output
64
VS
Output
EP
Exposed Pad
Description
Sync on Green Input. Used in embedded synchronization mode.
Analog Video Input Channels.
ADC Capacitor Network. See Figure 9 for a recommended capacitor network for
these pins.
Analog Supply Voltage (3.3 V).
Internal Voltage Reference Output. See Figure 9 for a recommended capacitor network
for this pin.
Common-Mode Level Pin for the Internal ADCs. See Figure 9 for a recommended
capacitor network for this pin.
ADC Capacitor Network. See Figure 9 for a recommended capacitor network for this pin.
Sync on Luma Input. Used in embedded synchronization mode.
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required
to reset the ADV7181D circuitry.
This pin selects the I2C address for the ADV7181D control and VBI readback ports. When
set to Logic 0, this pin sets the address for a write to Control Port 0x40 and the readback
address for VBI Port 0x21. When set to Logic 1, this pin sets the address for a write to
Control Port 0x42 and the readback address for VBI Port 0x23.
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input. Maximum clock rate of 400 kHz.
Vertical Synchronization Input Signal. This pin can be configured in CP mode to extract
timing in a 5-wire mode.
Horizontal Synchronization Input Signal (HS_IN). This pin can be configured in CP mode
to extract timing in a 5-wire mode.
Composite Synchronization Input Signal (CS_IN). This pin can be configured in CP mode
to extract timing in a 4-wire mode.
Field Synchronization Output Signal (FIELD). Used in all interlaced video modes.
Data Enable Signal (DE). This pin can also be used as a data enable (DE) signal in CP mode
to allow direct connection to an HDMI/DVI transmitter IC.
Vertical Synchronization Output Signal (SDP and CP Modes).
The exposed pad must be connected to GND.
Rev. 0 | Page 11 of 24
 

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