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ADV7181CBSTZ View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADV7181CBSTZ Datasheet PDF : 20 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADV7181C
Pin No.
51
20
22
21
30
9
Mnemonic
RESET
LLC
XTAL
XTAL1
ELPF
SFL/SYNC_OUT
41
REFOUT
42
CML
38, 39
CAPY1, CAPY2
44
CAPC2
56
HS_IN/CS_IN
55
50
29
33, 45
VS_IN
SOG/SOY
PWRDWN
NC
1 G = ground, I = input, O = output, I/O = input/output.
Type 1
I
O
I
O
O
O
O
O
I
I
I
I
I
I
Description
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is
required to reset the ADV7181C circuitry.
Line-Locked Output Clock. This pin is for the pixel data (the range is
12.825 MHz to 110 MHz).
Input pin for 28.63636 MHz crystal, or can be overdriven by an external 3.3 V,
28.63636 MHz clock oscillator source to clock the ADV7181C.
This pin should be connected to the 28.63636 MHz crystal or left as a no connect if
an external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the
ADV7181C. In crystal mode, the crystal must be a fundamental crystal.
The recommended external loop filter must be connected to this ELPF pin.
SFL: Subcarrier Frequency Lock. This pin contains a serial output stream that
can be used to lock the subcarrier frequency when this decoder is connected
to any Analog Devices digital video encoder.
SYNC_OUT: Sliced Synchronization Output Signal Available Only in CP Mode.
Internal Voltage Reference Output. See Figure 5 for a recommended capacitor
network for this pin.
Common-Mode Level Pin (CML) for the Internal ADCs. See Figure 5 for a
recommended capacitor network for this pin.
ADC Capacitor Network. See Figure 5 for a recommended capacitor network for
this pin.
ADC Capacitor Network. See Figure 5 for a recommended capacitor network for
this pin.
This pin can be configured in CP mode to be either a digital HS input signal or a
digital CS input signal used to extract timing in a 5-wire or 4-wire RGB mode.
VS Input Signal. Used in CP mode for 5-wire timing mode.
Sync on Green/Sync on Luma Input. Used in embedded synchronization mode.
A Logic 0 on this pin places the ADV7181C in a power-down mode.
No Connect. These pins are not connected internally.
Rev. 0 | Page 10 of 20
 

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