Drive Strength Selection (Clock)
DR_STR_C[1:0] Address 0x0E, [3:2]
The DR_STR_C[1:0] bits can be used to select the strength of
the clock signal output driver (LLC pin). For more information,
refer to the following sections:
• Drive Strength Selection (Sync)
• Drive Strength Selection (Data)
Table 20. DR_STR Function
DR_STR[1:0]
Description
00
Low drive strength (1×).
01*
Medium low drive strength (2×).
10
Medium high drive strength (3×).
11
High drive strength (4×).
*Default value.
Drive Strength Selection (Sync)
DR_STR_S[1:0] Address 0x0E, [1:0]
The DR_STR_S[1:0] bits allow the user to select the strength of
the synchronization signals with which HS, VS, and F are
driven. For more information, refer to the following sections:
• Drive Strength Selection (Data)
Table 21. DR_STR Function
DR_STR[1:0]
Description
00
Low drive strength (1×).
01*
Medium low drive strength (2×).
10
Medium high drive strength (3×).
11
High drive strength (4×).
*Default value.
ADV7181
Enable Subcarrier Frequency Lock Pin
EN_SFL_PIN Address 0x04, [1]
The subcarrier frequency lock pin (SDP, output only) has a
double function: it can also output raw sync-related information
(SogOut). The EN_SFL_PIN bit enables the output of
subcarrier lock information (also known as GenLock) from the
SDP core to an encoder in a decoder-encoder back-to-back
arrangement.
Table 22. EN_SFL_PIN
EN_SFL_PIN Description
0*
Subcarrier frequency lock output is disabled.
1
Subcarrier frequency lock information is
presented on the SFL pin.
*Default value.
Polarity LLC Pin
PCLK Address 0x37, [0]
The polarity of the clock that leaves the ADV7181 via the LLC
pin can be inverted using the PCLK bit. Note that this inversion
affects the clock for SDP.
Changing the polarity of the LLC clock output may be
necessary to meet the setup-and-hold time expectations of
follow-on chips.
Table 23. PCLK Function
PCLK
Description
0
Invert LLC output polarity.
1*
LLC output polarity normal (as per the Timing
Diagrams)
*Default value.
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