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ADV7172KST View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADV7172KST Datasheet PDF : 60 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADV7172/ADV7173
t3
SDATA
t5
t3
t6
t1
SCLOCK
t2
t7
t4
t8
Figure 1. MPU Port Timing Diagram
CLOCK
t9 t10
t12
CONTROL
I / PS
HSYNC,
FIELD/VSYNC,
BLANK
CONTROL
O / PS
PIXEL INPUT
DATA
Cb
Y
Cr
Y
Cb
Y
HSYNC,
FIELD/VSYNC,
BLANK,
CSO_HSO,
VSO, CLAMP
t11
t13
t14
Figure 2. Pixel and Control Data Timing Diagram
TTXREQ
t16
CLOCK
t17
TTX
t18
4 CLOCK
CYCLES
4 CLOCK
CYCLES
4 CLOCK
CYCLES
Figure 3. Teletext Timing Diagram
3 CLOCK
CYCLES
4 CLOCK
CYCLES
DAC Average Current Consumption
DAC D, E, F: The average current consumed by each DAC is the DAC output current as determined by RSET2/VREF (see Appendix 8).
DAC A, B, C: In normal power mode the average current consumed by each DAC is the DAC output current as determined by RSET1
(see Appendix 8).
In Low Power Mode the average current consumed by each DAC is approximately half the DAC output current as determined by RSET1.
Consult AN-551 for detailed information on ADV7172/ADV7173 power management.
–8–
REV. B
 

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