ADV7170/ADV7171
TR17
TR16
TR15
TR14
TR13
TR12
TR11
TR10
HSYNC TO PIXEL
DATA ADJUST
TR17 TR16
0
0 0 × TPCLK
0
1 1 × TPCLK
1
0 2 × TPCLK
1
1 3 × TPCLK
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
TR15 TR14
x
0
x
1
TC
TB
TB + 32μs
VSYNC WIDTH
(MODE 2 ONLY)
TR15 TR14
0
0 1 × TPCLK
0
1 4 × TPCLK
1
0 16 × TPCLK
1
1 128 × TPCLK
HSYNC TO
FIELD/VSYNC DELAY
TR13 TR12
00
01
10
11
TB
0 × TPCLK
4 × TPCLK
8 × TPCLK
16 × TPCLK
HSYNC WIDTH
TR11 TR10
TA
0
0 1 × TPCLK
0
1 4 × TPCLK
1
0 16 × TPCLK
1
1 128 × TPCLK
TIMING MODE 1 (MASTER/PAL)
LINE 1
HSYNC
TA
TB
LINE 313
TC
LINE 314
FIELD/VSYNC
Figure 44. Timing Register 1
SUBCARRIER FREQUENCY REGISTERS 0 TO 3
(FSC3 TO FSC0)
(Address [SR4 to SR00] = 09H to 0CH)
These 8-bit-wide registers are used to set up the subcarrier
frequency. The value of these registers is calculated by using
the following equation, rounded to the nearest integer:
No. of Subcarrier Frequency Values in One Line of Video Line × 232
No. of 27 MHz Clock Cycles in OneVideoLine
For example, in NTSC mode,
Subcarrier FrequencyValue = 227.5 × 232 = 569408542d = 21F07C1Fh
1716
Note that on power-up, FSC Register 0 is set to 16h. A value of 1F
as derived above is recommended.
Program as follows:
FSC Register 0: 1FH
FSC Register 2: 7CH
FSC Register 3: F0H
FSC Register 4: 21H
Figure 45 shows how the frequency is set up by the four registers.
SUBCARRIER
FREQUENCY FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0
REG 0
SUBCARRIER
FREQUENCY FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8
REG 1
SUBCARRIER
FREQUENCY FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16
REG 2
SUBCARRIER
FREQUENCY FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
REG 3
Figure 45. Subcarrier Frequency Register
SUBCARRIER PHASE REGISTERS (FP7 TO FP0)
(Address [SR4 to SR0] = 0DH)
This 8-bit-wide register is used to set up the subcarrier phase.
Each bit represents 1.41°. For normal operation this register is
set to 00Hex.
CLOSED CAPTIONING EVEN FIELD DATA
REGISTER 1 TO 0 (CED15 TO CED0)
(Address [SR4–SR0] = 0E to 0FH)
These 8-bit-wide registers are used to set up the closed
captioning extended data bytes on even fields. Figure 46
shows how the high and low bytes are set up in the registers.
BYTE 1 CED15 CED14 CED13 CED12 CED11 CED10 CED9 CED8
BYTE 0 CED7 CED6 CED5 CED4 CED3 CED2 CED1 CED0
Figure 46. Closed Captioning Extended Data Register
CLOSED CAPTIONING ODD FIELD DATA
REGISTERS 1 TO 0 (CCD15 TO CCD0)
(Subaddress [SR4 to SR0] = 10H to 11H)
These 8-bit-wide registers are used to set up the closed
captioning data bytes on odd fields. Figure 47 shows how the
high and low bytes are set up in the registers.
BYTE 1 CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD9 CCD8
BYTE 0 CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0
Figure 47. Closed Captioning Data Register
Rev. C | Page 35 of 64