ADV7171KSZ View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADV7171KSZ

Digital PAL/NTSC Video Encoder with 10-Bit SSAF™ and Advanced Power Management

Analog Devices 

ADV7170/ADV7171

REGISTER PROGRAMMING

This section describes each register, including subaddress

register, mode registers, subcarrier frequency registers,

subcarrier phase register, timing registers, closed captioning

extended data registers, closed captioning data registers, and

NTSC pedestal control registers, in terms of its configuration.

SUBADDRESS REGISTER (SR7 TO SR0)

The communications register is an 8-bit, write-only register.

After the part has been accessed over the bus and a read/write

operation is selected, the subaddress is set up. The subaddress

register determines to/from which register the operation takes

place.

Figure 37 shows the various operations under the control of the

subaddress register. Zero should always be written to SR7 to SR6.

REGISTER SELECT (SR5 TO SR0)

These bits are set up to point to the required starting address.

MODE REGISTER 0 MR0 (MR07 TO MR00)

(Address [SR4 to SR0] = 00H)

Figure 38 shows the various operations under the control of

Mode Register 0. This register can be read from as well as

written to.

MR0 BIT DESCRIPTION

Output Video Standard Selection (MR01 to MR00)

These bits are used to set up the encode mode. The ADV7170/

ADV7171 can be set up to output NTSC, PAL B/D/G/H/I, and

PAL M/N standard video.

Luminance Filter Control (MR02 to MR04)

These bits specify which luma filter is to be selected. The filter

selection is made independent of whether PAL or NTSC is

selected.

Chrominance Filter Control (MR05 to MR07)

These bits select the chrominance filter. A low-pass filter can be

selected with a choice of cutoff frequencies, 0.65 MHz,

1.0 MHz, 1.3 MHz, or 2 MHz, along with a choice of CIF

or QCIF filters.

WRITE

SEQUENCE

S

SLAVE ADDR

A(S)

SUBADDR

A(S)

LSB = 0

DATA

A(S)

LSB = 1

DATA

A(S) P

READ

SEQUENCE

S SLAVE ADDR A(S)

SUBADDR

A(S) S SLAVE ADDR A(S)

DATA

A(M)

S = START BIT

P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

A (S) = NO-ACKNOWLEDGE BY SLAVE

A (M) = NO-ACKNOWLEDGE BY MASTER

Figure 36. Write and Read Sequences

DATA

A(M) P

Rev. C | Page 28 of 64

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