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ADS8504IBDWRG4 View Datasheet(PDF) - Burr-Brown -> Texas Instruments

Part NameDescriptionManufacturer
ADS8504IBDWRG4 12-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER BB
Burr-Brown -> Texas Instruments BB
ADS8504IBDWRG4 Datasheet PDF : 19 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADS8504
www.ti.com
SLAS434 – JUNE 2005
BASIC OPERATION (continued)
CS and R/C are internally ORed and level triggered. There is not a requirement which input goes low first when
initiating a conversion. If, however, it is critical that CS or R/C initiates conversion n, be sure the less critical input
is low at least 10 ns prior to the initiating input.
To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. The
parallel output becomes active whenever R/C goes high. Refer to the READING DATA section.
Table 1. Control Line Functions for Read and Convert
CS
R/C
BUSY
OPERATION
1
X
X
None. Databus is in Hi-Z state.
0
1
Initiates conversion n. Databus remains in Hi-Z state.
0
1
Initiates conversion n. Databus enters Hi-Z state.
0
1
Conversion n completed. Valid data from conversion n on the databus.
1
1
Enables databus with valid data from conversion n.
1
0
Enables databus with valid data from conversion n-1(1). Conversion n in progress.
0
0
Enables databus with valid data from conversion n-1(1). Conversion n in progress.
0
0
New conversion initiated without acquisition of a new signal. Data is invalid. CS and/or R/C
must be high when BUSY goes high.
X
X
0
New convert commands ignored. Conversion n in progress.
(1) See Figure 19 and Figure 20 for constraints on data valid from conversion n-1.
200
33.2 k
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
1
28
2
27
+
3
26
2.2 µF
2.2 µF +
4
25
5
24
6
23
7
22
ADS8504
8
21
9
20
10
19
11
18
12
17
13
16
14
15
+
0.1 µF
+ +5V
10 µF
BUSY
R/C
Convert Pulse
DZ Low
DZ Low
DZ Low
DZ Low
D0 (LSB)
D1
D2
D3
40 ns Min
Figure 17. Basic Operation
READING DATA
The ADS8504 outputs full or byte-reading parallel data in binary 2's complement data output format. The parallel
output is active when R/C (pin 24) is high and CS (pin 25) is low. Any other combination of CS and R/C 3-states
the parallel output. Valid conversion data can be read in a full parallel, 12-bit word or two 8-bit bytes on pins 6-13
and pins 15-22. BYTE (pin 23) can be toggled to read both bytes within one conversion cycle. Refer to Table 2
for ideal output codes and Figure 18 for bit locations relative to the state of BYTE.
9
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