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ADS8504IBDWRG4 View Datasheet(PDF) - Burr-Brown -> Texas Instruments

Part NameDescriptionManufacturer
ADS8504IBDWRG4 12-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER BB
Burr-Brown -> Texas Instruments BB
ADS8504IBDWRG4 Datasheet PDF : 19 Pages
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ADS8504
SLAS434 – JUNE 2005
Typical Characteristics (continued)
20
0
−20
−40
−60
−80
−100
−120
−140
−160
0
25
20
8192 Points
0 fs = 250 KSPS
fi = 45 kHz, 0dB
−20 SINAD = 73.62 dB
THD = −94.03 dB
−40
−60
−80
−100
−120
−140
−160
0
25
FFT
50
75
f − Frequency − Hz
Figure 15.
FFT
50
75
f − Frequency − Hz
Figure 16.
www.ti.com
8192 Points
fs = 250 KSPS
fi = 1 kHz, 0dB
SINAD = 73.47 dB
THD = −94.03 dB
100
125
100
125
BASIC OPERATION
Figure 17 shows a basic circuit to operate the ADS8504 with a full parallel data output. Taking R/C (pin 24) low
for a minimum of 40 ns (1.75 µs max if BUSY is used to latch the data) initiates a conversion. BUSY (pin 26)
goes low and stays low until the conversion is completed and the output registers are updated. Data is output in
binary 2's complement with the MSB on pin 6. BUSY going high can be used to latch the data. All convert
commands are ignored while BUSY is low.
The ADS8504 begins tracking the input signal at the end of the conversion. Allowing 4 µs between convert
commands assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors
compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the
Calibration section).
STARTING A CONVERSION
The combination of CS (pin 25) and R/C (pin 24) low for a minimum of 40 ns immediately puts the sample/hold of
the ADS8504 in the hold state and starts conversion n. BUSY (pin 26) goes low and stays low until conversion n
is completed and the internal output register has been updated. All new convert commands during BUSY low are
ignored. CS and/or R/C must go high before BUSY goes high or a new conversion is initiated without sufficient
time to acquire a new signal.
The ADS8504 begins tracking the input signal at the end of the conversion. Allowing 4 µs between convert
commands assures accurate acquisition of a new signal. Refer to Table 1 for a summary of CS, R/C, and BUSY
states and Figure 19, Figure 20, and Figure 21 for the timing diagrams.
8
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