Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

ADS8504IBDWRG4 View Datasheet(PDF) - Burr-Brown -> Texas Instruments

Part NameDescriptionManufacturer
ADS8504IBDWRG4 12-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER BB
Burr-Brown -> Texas Instruments BB
ADS8504IBDWRG4 Datasheet PDF : 19 Pages
First Prev 11 12 13 14 15 16 17 18 19
ADS8504
SLAS434 – JUNE 2005
www.ti.com
REF
REF (pin 3) is an input for an external reference or the output for the internal 2.5-V reference. A 2.2-µF capacitor
should be connected as close to the REF pin as possible. The capacitor and the output resistance of REF create
a low-pass filter to bandlimit noise on the reference. Using a smaller value capacitor introduces more noise to the
reference degrading the SNR and SINAD. The REF pin should not be used to drive external ac or dc loads.
The range for the external reference is 2.3 V to 2.7 V and determines the actual LSB size. Increasing the
reference voltage increases the full-scale range and the LSB size of the converter which can improve the SNR.
CAP
CAP (pin 4) is the output of the internal reference buffer. A 2.2-µF capacitor should be placed as close to the
CAP pin as possible to provide optimum switching currents for the CDAC throughout the conversion cycle and
compensation for the output of the internal buffer. Using a capacitor any smaller than 1 µF can cause the output
buffer to oscillate and may not have sufficient charge for the CDAC. Capacitor values larger than 2.2 µF have
little affect on improving performance. The ESR (equivalent series resistance) of these compensation capacitors
is also critical. Keep the total ESR under 3 . See the TYPICAL CHARACTERISTICS section for how
performance is affected by ESR.
The output of the buffer is capable of driving up to 2 mA of current to a dc load. A dc load requiring more than 2
mA of current from the CAP pin begins to degrade the linearity of the ADS8504. Using an external buffer allows
the internal reference to be used for larger dc loads and ac loads. Do not attempt to directly drive an ac load with
the output voltage on CAP. This causes performance degradation of the converter.
LAYOUT
POWER
For optimum performance, tie the analog and digital power pins to the same +5-V power supply and tie the
analog and digital grounds together. As noted in the electrical specifications, the ADS8504 uses 90% of its power
for the analog circuitry. The ADS8504 should be considered as an analog component.
The +5-V power for the A/D should be separate from the +5 V used for the system's digital logic. Connecting
VDIG (pin 28) directly to a digital supply can reduce converter performance due to switching noise from the digital
logic. For best performance, the +5-V supply can be produced from whatever analog supply is used for the rest
of the analog signal conditioning. If +12-V or +15-V supplies are present, a simple +5-V regulator can be used.
Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter
the supply. Either using a filtered digital supply or a regulated analog supply, both VDIG and VANA should be tied
to the same +5-V source.
GROUNDING
Three ground pins are present on the ADS8504. DGND is the digital supply ground. AGND2 is the analog supply
ground. AGND1 is the ground which all analog signals internal to the A/D are referenced. AGND1 is more
susceptible to current induced voltage drops and must have the path of least resistance back to the power
supply.
All the ground pins of the A/D should be tied to the analog ground plane, separated from the system's digital
logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to the
system ground as near to the power supplies as possible. This helps to prevent dynamic digital ground currents
from modulating the analog ground through a common impedance to power ground.
SIGNAL CONDITIONING
The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of
charge injection which can cause the driving op amp to oscillate. The FET switch on the ADS8504, compared to
the FET switches on other CMOS A/D converters, releases 5%-10% of the charge. There is also a resistive front
end which attenuates any charge which is released. The end result is a minimal requirement for the anti-alias
filter on the front end. Any op amp sufficient for the signal in an application is sufficient to drive the ADS8504.
The resistive front end of the ADS8504 also provides an assured ±25-V overvoltage protection. In most cases,
this eliminates the need for external input protection circuitry.
14
Direct download click here

 

Share Link : 
All Rights Reserved© datasheetq.com 2015 - 2020  ] [ Privacy Policy ] [ Request Datasheet  ] [ Contact Us ]