SLAS434 – JUNE 2005
Pins 6 − 13 Hi−Z
Pins 15 − 18 Hi−Z
Figure 21. Using CS and BYTE to Control Data Bus
The ADS8504 offers a standard ±10-V input range. Figure 23 shows the necessary circuit connections for the
ADS8504 with and without hardware trim. Offset and full-scale error specifications are tested and specified with
the fixed resistors shown in Figure 23(b). Full-scale error includes offset and gain errors measured at both +FS
and -FS. Adjustments for offset and gain are described in the Calibration section of this data sheet.
The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors
compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the
The nominal input impedance of 11.5 kΩ results from the combination of the internal resistor network shown on
the front page of the product data sheet and the external resistors. The input resistor divider network provides
inherent overvoltage protection assured to at least ±25 V. The 1% resistors used for the external circuitry do not
compromise the accuracy or drift of the converter. They have little influence relative to the internal resistors, and
tighter tolerances are not required.
The input signal must be referenced to AGND1. This will minimize the ground loop problem typical to analog
designs. The analog input should be driven by a low impedance source. A typical driving circuit using OPA627 or
OPA132 is shown in Figure 6.
Pin 7 Pin 1
Pin 2 −
Figure 22. Typical Driving Circuitry (±10 V, No Trim)