Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

ADS7866 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
ADS7866 1.2-V, 12-/10-/8-BIT, 200-KSPS/100-KSPS, MICRO-POWER, MINIATURE ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE TI
Texas Instruments TI
ADS7866 Datasheet PDF : 28 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
www.ti.com
ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
TIMING REQUIREMENTS(1)(2)
At –40°C to 85°C, fSCLK = 3.4 MHz if 1.6 V VDD 3.6 V; fSCLK = 1.7 MHz if 1.2 V VDD < 1.6 V, 50-pF Load on SDO Pin,
unless otherwise noted
tsample
tconvert
PARAMETER
Sample time
Conversion time
tC(SCLK)
Cycle time
tWH(SCLK)
tWL(SCLK)
Pulse duration
Pulse duration
tSU(CSF-FSCLKF)
Setup time
tD(CSF-SDOVALID)
Delay time
tH(SCLKF-SDOVALID) Hold time
tD(SCLKF-SDOVALID) Delay time
tDIS(EOC-SDOZ)
Disable time
tWH(CS)
Pulse duration
tSU(LSBZ-CSF)
Setup time
TEST CONDITIONS
ADS7866
ADS7867
ADS7868
1.2 V VDD < 1.6 V
1.6 V VDD < 1.8 V
1.8 V VDD < 2.5 V
2.5 V VDD 3.6 V
1.2 V VDD < 1.6 V
1.6 V VDD < 1.8 V
1.8 V VDD 3.6 V
1.2 V VDD < 1.6 V
1.6 V VDD < 1.8 V
1.8 V VDD 3.6 V
1.2 V VDD < 1.6 V
1.6 V VDD < 1.8 V
1.8 V VDD 3.6 V
1.2 V VDD < 1.6 V
1.6 V VDD < 1.8 V
1.8 V VDD 3.6 V
1.2 V VDD < 1.6 V
1.6 V VDD < 1.8 V
1.8 V VDD 3.6 V
1.2 V VDD < 1.6 V
1.6 V VDD < 1.8 V
1.8 V VDD 3.6 V
1.2 V VDD < 1.6 V
1.6 V VDD < 1.8 V
1.8 V VDD 3.6 V
MIN
See (3)
See (3)
See (3)
See (3)
0.4 × tC(SCLK)
0.4 × tC(SCLK)
192
55
55
TYP
tSU(CSF-FSCLKF) + 2 × tC(SCLK)
13 × tC(SCLK)
11 × tC(SCLK)
9 × tC(SCLK)
20
10
10
10
7
7
20
10
10
20
10
10
MAX
100
100
50
6.7
0.6 × tC(SCLK)
0.6 × tC(SCLK)
65
55
55
140
140
140
80
60
60
UNIT
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See timing diagram in Figure 1.
(3) Min tC(SCLK) is determined by the Min tSAMPLE of the specific resolution and supply voltage. See Acquisition Time, Conversion Time, and
Total Cycle Time section for further details.
SCLK
tSU(CSF−FSCLKF)
CS
SDO
Hi−Z
Auto Power−Down
HOLD tC(SCLK)
tWH(SCLK)
1
2
3
4
5
678
tWL(SCLK)
EOC Last SCLK= 16 for ADS 7866
14for ADS 7867
16
9
10
14
12
12for ADS 7868
tWH(CS)
tSAMPLE
tCONVERT
tD(CSF−SDOVALID)
tH(SCLKF−SDOVALID)
tD(SCLKF−SDOVALID)
“0” “0” “0” “0”
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5
tCYCLE
tSU(LSBZ−CSF)
tDIS(EOC−SDOZ)
Hi−Z
LSB
Auto Power− Down
tSU(CSF−FSCLKF)
1
2
tD(CSF−SDOVALID)
“0” “0” “0”
Figure 1. Timing Diagram
9
Direct download click here

 

Share Link : 
All Rights Reserved© datasheetq.com 2015 - 2019  ] [ Privacy Policy ] [ Request Datasheet  ] [ Contact Us ]