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ADS7866 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
ADS7866 1.2-V, 12-/10-/8-BIT, 200-KSPS/100-KSPS, MICRO-POWER, MINIATURE ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE TI
Texas Instruments TI
ADS7866 Datasheet PDF : 28 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
www.ti.com
ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
SPECIFICATIONS, ADS7868
At –40°C to 85°C, fSAMPLE = 280 KSPS and fSCLK = 3.4 MHz if 1.6 V VDD 3.6 V; fSAMPLE = 140 KSPS and fSCLK = 1.7 MHz if
1.2 V VDD < 1.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SYSTEM PERFORMANCE
Resolution
8
Bits
No missing codes
8
Bits
Integral linearity
–0.5
0.5 LSB(1)
Differential linearity
–0.5
0.5 LSB
Offset error(2)
1.2 V VDD < 1.6 V
1.6 V VDD 3.6 V
Gain error(3)
1.2 V VDD < 1.6 V
1.6 V VDD 3.6 V
Total unadjusted error(4)
1.2 V VDD < 1.6 V
1.6 V VDD 3.6 V
SAMPLING DYNAMICS (See Timing Characteristics Section)
–0.5
0.5
LSB
–0.5
0.5
–0.5
0.5
LSB
–0.5
0.5
–1
1
LSB
–1
1
tCONVERT
tSAMPLE
fSAMPLE
Conversion time
Acquisition time
Throughput rate
Aperture delay
fSCLK = 3.4 MHz, 9 SCLK cycles
fSCLK = 3.4 MHz, 1.6 V VDD 3.6 V
fSCLK = 3.4 MHz, 1.6 V VDD 3.6 V
2.647
0.64
µs
µs
280 KSPS
10
ns
Aperture jitter
40
ps
DYNAMIC CHARACTERISTICS
SINAD
Signal-to-noise
and distortion
SNR
Signal-to-noise ratio
THD
SFDR
Total harmonic
distortion (5)
Spurious free dynamic
range
Full-power bandwidth(6)
ANALOG INPUT
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V VDD < 1.6 V
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V VDD 3.6 V
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V VDD < 1.6 V
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V VDD 3.6 V
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V VDD < 1.6 V
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V VDD 3.6 V
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V VDD < 1.6 V
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V VDD 3.6 V
At 0.1 dB, 1.2 V VDD < 1.6 V
At 0.1 dB, 1.6 V VDD 3.6 V
At 3 dB, 1.2 V VDD < 1.6 V
At 3 dB, 1.6 V VDD 3.6 V
49
49
49.4
49.4
49.8
–65
–72
67
66
67
2
4
3
8
dB
dB
dB
-66
dB
MHz
Full-scale input span(7) VIN – GND
CS
Input capacitance
Input leakage current
0
VDD
V
12
pF
–1
1 µA
DIGITAL INPUT
Logic family, CMOS
1.2 V VDD < 1.6 V
VIH
Input logic high level
1.6 V VDD < 1.8 V
1.8 V VDD < 2.5 V
2.5 V VDD 3.6 V
0.7×VDD
0.7×VDD
0.7×VDD
2
3.6
3.6
V
3.6
3.6
(1) LSB = Least Significant BIt
(2) The difference in the first code transition 000...000 to 000...001 from the ideal value of GND + 1 LSB.
(3) The difference in the last code transition 011...111 to 111...111 from the ideal value of VDD - 1 LSB with the offset error removed.
(4) The absolute difference from the ideal transfer function of the converter. This specification is similar to INL error except the effects of
offset error and gain error are included.
(5) The 2nd through 10th harmonics are used to determine THD.
(6) Input frequency where the amplitude of the digitized signal has decreased by 0.1 dB or 3 dB.
(7) Ideal input span which does not include gain or offset errors.
7
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