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ADS7866 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
ADS7866 1.2-V, 12-/10-/8-BIT, 200-KSPS/100-KSPS, MICRO-POWER, MINIATURE ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE TI
Texas Instruments TI
ADS7866 Datasheet PDF : 28 Pages
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THEORY OF OPERATION
ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
The ADS7866/67/68 is a family of low supply voltage, low power, high-speed successive approximation register
(SAR) analog-to-digital converters (ADCs). The devices can be operated from a supply range from 1.2 V to 3.6
V. There is no need for an external reference. The reference is derived internally from the supply voltage, so the
analog input range can be from 0 V to VDD. These ADCs use a charge redistribution architecture, which
inherently includes a sample/hold function.
START OF A CONVERSION CYCLE
A conversion cycle is initiated by bringing the CS pin low and supplying the serial clock SCLK. The time between
the falling edge of CS and the third falling edge of SCLK after CS falls is used to acquire the input signal. This
must be greater than or equal to the minimum acquisition time (MIN tSAMPLE in Table 1) specified for the desired
resolution and supply voltage. On the third falling edge of SCLK after CS falls, the device goes into hold mode
and the process of digitizing the sampled input signal starts.
Acquisition Time, Conversion Time, and Total Cycle Time
The maximum SCLK frequency is determined by the minimum acquisition time (MIN tSAMPLE) specified for the
specific resolution and supply voltage of the device. The conversion time is determined by the frequency of SCLK
since this is a synchronous converter. The conversion time is 13 times the SCLK cycle time tC(SCLK) for the
ADS7866, 11 times for the ADS7867, and 9 times for the ADS7868. The acquisition time, which is also the
power up time, is the set-up time between the first falling edge of SCLK after CS falls (tSU(CSF-FSCLKF)) plus 2
times tC(SCLK).
The total cycle time, tCYCLE, which is the inverse of the maximum sample rate, can be calculated as follows:
tCYCLE = tSAMPLE + tCONVERT + 0.5 × tC(SCLK)
if tDIS(EOC-SDOZ) + tSU(LSBZ-CSF) 0.5 × tC(SCLK)
tCYCLE = tSAMPLE + tCONVERT + tDIS(EOC-SDOZ) + tSU(LSBZ-CSF)
if tDIS(EOC-SDOZ) + tSU(LSBZ-CSF) > 0.5 × tC(SCLK)
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