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ADS7866 데이터 시트보기 (PDF) - Burr-Brown -> Texas Instruments

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ADS7866 1.2-V, 12-/10-/8-BIT, 200-KSPS/100-KSPS, MICRO-POWER, MINIATURE ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE BB
Burr-Brown -> Texas Instruments BB
ADS7866 Datasheet PDF : 28 Pages
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ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
www.ti.com
The serial output SDO is activated on the falling edge of CS. The first leading zero is available on SDO until the
first falling edge of SCLK after CS falls. The remaining 3 leading zeros are shifted out on SDO on the first,
second, and third falling edges of SCLK after CS falls. The MSB of the converted result follows 4 leading zeros
and is clocked out on the fourth falling edge of SCLK. The rising edge of CS or the falling edge of SCLK when
the EOC occurs puts SDO output into 3-state. Refer to Table 2 for ideal output codes versus input voltages.
Table 2. ADS7866/67/68 Ideal Output Codes Versus Input Voltages
DESCRIPTION
ADS7866
Least Significant Bit (LSB)
Full Scale
Midscale
Midscale – 1LSB
Zero
ADS7867
Least Significant Bit (LSB)
Full Scale
Midscale
Midscale – 1LSB
Zero
ADS7868
Least Significant Bit (LSB)
Full Scale
Midscale
Midscale – 1LSB
Zero
ANALOG INPUT VOLTAGE
VDD/4096
VDD – 1LSB
VDD/2
VDD/2 – 1LSB
0V
VDD/1024
VDD – 1LSB
VDD/2
VDD/2 – 1LSB
0V
VDD/256
VDD – 1LSB
VDD/2
VDD/2 – 1LSB
0V
DIGITAL OUTPUT STRAIGHT BINARY
BINARY CODE
HEX CODE
1111 1111 1111
FFF
1000 0000 0000
800
0111 1111 1111
7FF
0000 0000 0000
000
11 1111 1111
3FF
10 0000 0000
200
01 1111 1111
1FF
00 0000 0000
000
1111 1111
FF
1000 0000
80
0111 1111
7F
0000 0000
00
POWER DISSIPATION
The ADS7866/67/68 family is capable of operating with very low supply voltages while drawing a fraction of a
milliamp. Furthermore, there is an auto power-down mode to reduce the power dissipation between conversion
cycles. Carefully selected system design can take advantage of these features to achieve optimum power
performance.
Auto Power-Down Mode
The ADS7866/67/68 family has an auto power-down feature. Besides powering down all circuitry, the converter
consumes only 8 nA typically in this mode. The device automatically wakes up when CS falls. However, not all of
the functional blocks are fully powered until sometime before the third falling edge of SCLK. The device powers
down once it reaches the end of conversion (EOC) which is the 16th falling edge of SCLK for the ADS7866 (the
14th and 12th for the ADS7867 and ADS7868, respectively). If CS is pulled high before the device reaches the
EOC, the converter goes into power-down mode and the ongoing conversion is aborted. Refer to the timing
diagram in Figure 1 for further information.
Power Saving: SCLK Frequency and Throughput
These converters achieve lower power dissipation for a fixed throughput rate fsample = 1/tcycle by using higher
SCLK frequencies. Higher SCLK frequencies reduce the acquisition time (tsample) and conversion time (tconvert).
This means the converters spend more time in auto power-down mode per conversion cycle. This can be
observed in Figure 8 which shows the ADS7866 supply current versus SCLK frequency for fsample = 100 KSPS.
For a particular SCLK frequency, the acquisition time and conversion time are fixed. Therefore, a lower
throughput increases the proportion of the time the converters are in power down. Figure 10 shows this case for
the ADS7866 power consumption versus throughput rate for fSCLK = 3.4 MHz.
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