SLAS465 – JUNE 2005
Figure 28 shows the analog input equivalent circuit for the ADS7866/67/68. The analog input is provided
between the VIN and GND pins. When a conversion is initiated, the input signal is sampled on the internal
capacitor array. When the converter enters hold mode, the input signal is captured on the internal capacitor
array. The VIN input range is limited to 0 V to VDD because the reference is derived from the supply.
The current flowing into the analog input depends upon a number of factors, such as the sample rate, the input
voltage, and the input source impedance. The current from the input source charges the internal capacitor array
during the sample period. After this capacitance has been fully charged, there is no further input current. The
source of the analog input voltage must be able to charge the input capacitance CS (12 pF typical) within the
minimum acquisition time (MIN tSAMPLE) specified for the desired resolution and supply voltage. In the case of the
ADS7866, the MIN tSAMPLE for 12-bit resolution is 643 ns (VDD between 1.6 V and 3.6 V). When the converter
goes into hold mode, the input impedance is greater than 1 GΩ.
Care must be taken regarding the absolute analog input voltage. In order to maintain the linearity of the
converter, the span (VIN – GND) should be within the limits specified. Outside of these limits, the converter’s
linearity may not meet specifications. Noise introduced into the converter from the input source may be
minimized by using low bandwidth input signals along with low-pass filters.
Device is in Hold Mode
Figure 28. Analog Input Equivalent Circuit (Typical Impedance Values at VDD = 1.6 V, TA = 27°C)
Choice of Input Driving Amplifier
The analog input to the converter needs to be driven with a low noise, low voltage op amp like the OPA364 or
OPA333. An RC filter is recommended at the input pin to low-pass filter the noise from the source. The input to
the converter is a unipolar input voltage in the range 0 V to VDD.
The ADS7866/67/68 interface with microprocessors or DSPs through a high-speed SPI compatible serial
interface with CPOL = 1 (inactive SCLK returns to logic high or SCLK leading edge is the rising edge), CPHA = 1
(output data changes on falling edge of SCLK and is available on the rising edge of SCLK). The sampling,
conversion, and activation of SDO are initiated on the falling edge of CS. The serial clock (SCLK) is used for
controlling the rate of conversion. It also provides a mechanism allowing synchronization with digital host
The digital inputs, CS and SCLK, can exceed the supply voltage VDD as long as they do not exceed the
maximum VIH of 3.6 V. This allows the ADS7866/67/68 family to interface with host processors which use a
different supply voltage than the converter without requiring external level-shifting circuitry. Furthermore, the
digital inputs can be applied to CS and SCLK before the supply voltage of the converter is activated without the
risk of creating a latch-up condition.
The ADS7866/67/68 outputs 12/10/8-bit data after 4 leading zeros, respectively. These codes are in straight
binary format as shown in Table 2.