ADS6422 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADS6422 Datasheet PDF : 75 Pages
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www.ti.com
DESCRIPTION OF PARALLEL PINS
ADS6445, ADS6444
ADS6443, ADS6442
SLAS531 – MAY 2007
SCLK
LOW
LOW
HIGH
HIGH
SDATA
LOW
HIGH
LOW
HIGH
Table 5. SCLK, SDATA Control Pins
DESCRIPTION
NORMAL conversion.
SYNC – ADC outputs sync pattern on all channels. This pattern can be used by the receiver to align the
deserialized data to the frame boundary. See Capture Test Patterns for details.
POWER DOWN – Global power down, all channels of the ADC are powered down, including internal references,
PLL and output buffers.
DESKEW – ADC outputs deskew pattern on all channels. This pattern can be used by the receiver to ensure
deserializer uses the right clock edge. See Capture Test Patterns for details.
Table 6. SEN Control Pin
SEN
0
(3/8)LVDD
(5/8)LVDD
LVDD
DESCRIPTION
External reference and 0 dB coarse gain (full-scale = 2 VPP)
External reference and 3.5 dB coarse gain (full-scale = 1.34 VPP)
Internal reference and 3.5 dB coarse gain (full-scale = 1.34 VPP)
Internal reference and 0 dB coarse gain (full-scale = 2 VPP)
Independent of the programming mode used, after power-up the parallel pins PDN, CFG1 to CFG4 will
automatically configure the device as per the voltage applied (refer to Table 7 to Table 11).
PDN
0
AVDD
Normal operation
Power down global
Table 7. PDN Control Pin
DESCRIPTION
CFG1
0
(3/8)LVDD
(5/8)LVDD
LVDD
Table 8. CFG1 Control Pin
DDR Bit clock and 1-wire interface
Not used
SDR Bit clock and 2-wire interface
DDR Bit clock and 2-wire interface
DESCRIPTION
CFG2
0
(3/8)LVDD
(5/8)LVDD
LVDD
Table 9. CFG2 Control Pin
DESCRIPTION
14x Serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock mode)
16x Serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock mode)
16x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode)
14x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode)
CFG3
Table 10. CFG3 Control Pin
RESERVED - TIE TO GROUND
CFG4
0
(3/8)LVDD
(5/8)LVDD
LVDD
Table 11. CFG4 Control Pin
MSB First and 2s complement
MSB First and offset binary
LSB First and offset binary
LSB First and 2s complement
DESCRIPTION
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