ADP1051-240-EVALZ View Datasheet(PDF) - Analog Devices
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ADP1051-240-EVALZ Datasheet PDF : 108 Pages
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ADP1051
Data Sheet
Manufacturer Specific Latched Flags
The ADP1051 has a set of latched flag registers (Register 0xFEA3 to
Register 0xFEA5). The latched flag registers have the same flags as
Register 0xFEA0 to Register 0xFEA2, but the flags in the latched
registers remain set so that intermittent faults can be detected.
Reading a latched flag register resets all the flags in that register.
A PSON signal can also reset the latched flags.
Flags Debounce Time
The debounce timing of the manufacturer specific flags and
the PMBus standard flags is programmable (see Table 6). The
debounce time is the time during which the fault condition
must be continuously triggered before the flag is set. Refer to
the corresponding register settings for more information.
The debounce time is used for flag setting. Only the PGOOD
flag has a debounce time for flag clearing. For all other flags,
the flag reenable delay, specified in Register 0xFE05[7:6] (see
Table 106), functions as the debounce time for flag clearing.
Refer to the Manufacturer Specific Protection Responses
section for details.
Housekeeping Flags
The CHIP_PASSWORD_UNLOCKED flag (Register 0xFEA0[7])
indicates that the chip password is in the unlocked state, and all
the registers can be accessed.
The VDD_OV flag (Register 0xFEA0[0]) is set when the VDD
voltage exceeds the VDD OVLO threshold. The debounce time is
programmable as 2 μs or 500 μs, using Register 0xFE05[4]. When
the flag is set, the ADP1051 shuts down. The flag is always cleared
when Register 0xFE05[5] is set, regardless of the VDD voltage.
The EEPROM_UNLOCKED flag (Register 0xFEA2[3]) indicates
that the EEPROM is in the unlocked state and can be updated.
The CRC_FAULT flag (Register 0xFEA2[2]) indicates that an error
has occurred when downloading the EEPROM contents to the
internal registers. The device shuts down and requires a PSON
signal (programmed in Register 0x01 and Register 0x02) and/or
the toggling of the CTRL pin (Pin 16) to restart.
Flag Blanking During Soft Start
Flag blanking means that when a fault condition is met, the
corresponding flag is set, but there are no related actions.
The following flags are always blanked during soft start:
VOUT_UV_FAULT
OT_FAULT
The following flags can be programmed to be blanked during soft
start, using Register 0xFE0B:
VOUT_OV_FAULT (Bit 0)
CS3_OC_FAULT (Bit 1)
IOUT_OC_FAULT (Bit 2)
IIN_OC_FAST_FAULT (Bit 3)
VIN_UV_FAULT (Bit 4)
LIGHT_LOAD (Bit 5)
DEEP_LIGHT_LOAD (Bit 5)
FLAGIN (Bit 6)
SR_RC_FAULT (Bit 7)
If a flag is blanked during soft start, it is also blanked during the
TON_DELAY time.
Table 6. Flag Debounce Time
Flag
VOUT_OV_FAULT
VOUT_UV_FAULT
IOUT_OC_FAULT
OT_FAULT
OT_WARNING
CS3_OC_FAULT
VIN_UV_FAULT
FLAGIN
SR_RC_FAULT
VDD_OV
PGOOD
Debounce Time
0 μs, 1 μs, 2 μs, 8 μs
0 ms, 20 ms, 40 ms, 80 ms, 160 ms, 320 ms, 640 ms, 1280 ms
0 ms, 20 ms, 40 ms, 80 ms, 160 ms, 320 ms, 640 ms, 1280 ms
1 sec
0 ms, 100 ms
0 ms, 10 ms, 20 ms, 200 ms
0 ms, 2.5 ms, 10 ms, 100 ms
0 μs, 100 μs
40 ns, 200 ns
2 μs, 500 μs
0 ms, 200 ms, 320 ms, 600 ms
Register
0xFE26[7:6]
0x45[2:0]
0x47[2:0]
0x50[2:0]
0xFE2F[2]
0xFE19[6:5]
0xFE29[1:0]
0xFE12[1]
0xFE1A[3]
0xFE05[4]
0xFE0E[3:0]
Rev. B | Page 30 of 108
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