Data Sheet
ADP1051
SYNI ENABLE
REG 0xFE12[3]
SYNI/FLGI
SYNI/FLGI
SELECTION
REG 0xFE12[0]
SYNI MODE
320ns
DEBOUNCE
POLARITY
REG 0xFE12[2]
FLGI MODE
SYNI DELAY
TIME SETTING
REG 0xFE11
0µs
DEBOUNCE
DEBOUNCE TIME
REG 0xFE12[1]
100µs
DEBOUNCE
±3.125%
PHASE CAPTURE
RANGE SELECTION
REG 0xFE12[6]
SYNC OPERATION
AS SLAVE DEVICE
±6.25%
FLAGIN FLAG
RESPONSE
REG 0xFE03[3:0]
OUTC
OUTD
SYNO ENABLE
REG 0xFE12[5:4]
OUTC IN SYNO MODE
OUTD IN SYNO MODE
Figure 18. Synchronization Configuration
Figure 19. Edge Adjustment Reference During Synchronization
To ensure a constant dead time before and after synchronization,
Register 0xFE6D to Register 0xFE6F can be set for edge adjustment
referred to tS/2 or tS. For example, the falling edge of OUTA (tF1) is
referred to the ½ × tS position, which means that the time difference
between tF1 and ½ × tS is a constant during synchronization
transition. Figure 19 shows an example of the edge adjustment
reference settings in a full bridge topology.
Synchronization as a Master Device
Register 0xFE12[5:4] can be used to program the synchronization
output (SYNO) function, in which the OUTC pin (Pin 11) or the
OUTD pin (Pin 12) generates a synchronization reference clock
output. When Bit 4 is set, OUTC generates a 640 ns pulse width
clock signal that represents the internal switching frequency. When
Bit 5 is set, OUTD generates a 640 ns pulse width clock signal that
also represents the internal switching frequency.
To compensate the propagation delays in the synchronization scheme
of the ADP1051, the synchronization output signal has a 760 ns lead
time before the start of the internal switching cycle.
The synchronization output signal is always available when VDD
is applied. The VDD_OV fault is the only fault condition that
suspends the synchronization output signal.
OUTPUT VOLTAGE SENSE AND ADJUSTMENT
The output voltage sense and adjustment function is used for
control, monitoring, and undervoltage protection of the remote
output voltage. VS− (Pin 1) and VS+ (Pin 2) are fully differential
inputs. The voltage sense point can be calibrated digitally to remove
any errors due to external components. This calibration can be
performed in the production environment, and the settings can
be stored in the EEPROM of the ADP1051 (see the Power Supply
Calibration and Trim section for more information).
For voltage monitoring, the READ_VOUT output voltage command
(Register 0x8B) is updated every 10 ms. The ADP1051 stores every
ADC sample for 10 ms and then calculates the average value at the
end of the 10 ms period. Therefore, if Register 0x8B is read at least
every 10 ms, a true average value is obtained. The voltage information
is available through the I2C/PMBus interface.
The control loop of the ADP1051 features a patented multipath
architecture. The output voltage is converted simultaneously by two
ADCs: a high accuracy ADC and a high speed ADC. The complete
signal is reconstructed and processed in the digital compensator
to provide a high performance and cost competitive solution.
Rev. B | Page 19 of 108