E28F001BX-B90 View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
E28F001BX-B90 Datasheet PDF : 33 Pages
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28F001BX-T 28F001BX-B
BUS OPERATION
Standby
Flash memory reads erases and writes in-system
via the local CPU All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles
Read
The 28F001BX has three read modes The memory
can be read from any of its blocks and information
can be read from the Intelligent Identifier or the
Status Register VPP can be at either VPPL or VPPH
CE at a logic-high level (VIH) places the 28F001BX
in standby mode Standby operation disables much
of the 28F001BX’s circuitry and substantially reduc-
es device power consumption The outputs (DQ0 –
DQ7) are placed in a high-impedance state indepen-
dent of the status of OE If the 28F001BX is dese-
lected during erase or program the device will
continue functioning and consuming normal active
power until the operation is completed
Deep Power-Down
The first task is to write the appropriate read mode
command to the Command Register (array Intelli-
gent Identifier or Status Register) The 28F001BX
automatically resets to Read Array mode upon initial
device powerup or after exit from deep powerdown
The 28F001BX has four control pins two of which
must be logically active to obtain data at the outputs
Chip Enable (CE ) is the device selection control
and when active enables the selected memory de-
vice Output Enable (OE ) is the data input output
(DQ0 – DQ7) direction control and when active
drives data from the selected memory onto the I O
bus RP and WE must also be at VIH Figure 12
illustrates read bus cycle waveforms
Output Disable
With OE at a logic-high level (VIH) the device out-
puts are disabled Output pins (DQ0 – DQ7) are
placed in a high-impedance state
The 28F001BX offers a 0 25 mW VCC power-down
feature entered when RP is at VIL During read
modes RP low deselects the memory places out-
put drivers in a high-impedance state and turns off
all internal circuits The 28F001BX requires time
tPHQV (see AC Characteristics-Read Only Opera-
tions) after return from power-down until initial mem-
ory access outputs are valid After this wakeup inter-
val normal operation is restored The Command
Register is reset to Read Array and the Status Reg-
ister is cleared to value 80H upon return to normal
operation
During erase or program modes RP low will abort
either operation Memory contents of the block be-
ing altered are no longer valid as the data will be
partially programmed or erased Time tPHWL after
RP goes to logic-high (VIH) is required before an-
other command can be written
Mode
Read
Output Disable
Standby
Deep Power Down
Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
Write
Table 2 28F001BX Bus Operations
Notes RP CE OE WE
123
VIH
VIL
VIL
VIH
2
VIH
VIL
VIH
VIH
2
VIH
VIH
X
X
2
VIL
X
X
X
234
VIH
VIL
VIL
VIH
2 3 4 5 VIH
VIL
VIL
VIH
2 6 7 8 VIH
VIL
VIH
VIL
A9 A0 VPP
XX X
XX X
DQ0 – 7
DOUT
High Z
XX X
High Z
XX X
High Z
VID VIL X
89H
VID VIH X 94H 95H
XX X
DIN
NOTES
1 Refer to DC Characteristics When VPP e VPPL memory contents can be read but not programmed or erased
2 X can be VIL or VIH for control pins and addresses and VPPL or VPPH for VPP
3 See DC Characteristics for VPPL VPPH VHH and VID voltages
4 Manufacturer and device codes may also be accessed via a Command Register write sequence Refer to Table 3 A1 – A8
A10 – A16 e VIL
5 Device ID e 94H for the 28F001BX-T and 95H for the 28F001BX-B
6 Command writes involving block erase or byte program are successfully executed only when VPP e VPPH
7 Refer to Table 3 for valid DIN during a write operation
8 Program or erase the boot block by holding RP at VHH or toggling OE to VHH See AC Waveforms for program erase
operations
7
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