E28F001BN-T70 View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

E28F001BN-T70

1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY

Intel 

28F001BX-T 28F001BX-B

PRINCIPLES OF OPERATION

The 28F001BX introduces on-chip write automation

to manage write and erase functions The write state

machine allows for 100% TTL-level control inputs

fixed power supplies during erasure and program-

ming minimal processor overhead with RAM-like

write timings and maximum EPROM compatiblity

After initial device powerup or after return from

deep powerdown mode (see Bus Operations) the

28F001BX functions as a read-only memory Manip-

ulation of external memory-control pins yield stan-

dard EPROM read standby output disable or Intelli-

gent Identifier operations Both Status Register and

Intelligent Identifiers can be accessed through the

Command Register when VPP e VPPL

This same subset of operations is also available

when high voltage is applied to the VPP pin In addi-

tion high voltage on VPP enables successful erasure

and programming of the device All functions associ-

ated with altering memory contents program

erase status and inteligent Identifier are accessed

via the Command Register and verified through the

Status Register

Commands are written using standard microproces-

sor write timings Register contents serve as input to

the WSM which controls the erase and program-

ming circuitry Write cycles also internally latch ad-

dresses and data needed for programming or erase

operations With the appropriate command written to

the register standard microprocessor read timings

output array data access the intelligent identifier

codes or output program and erase status for verifi-

cation

Interface software to initiate and poll progress of in-

ternal program and erase can be stored in any of the

28F001BX blocks This code is copied to and exe-

cuted from system RAM during actual flash memory

update After successful completion of program

and or erase code execution out of the 28F001BX

is again possible via the Read Array command

Erase suspend resume capability allows system

software to suspend block erase and read data exe-

cute code from any other block

Command Register and Write

Automation

An on-chip state machine controls block erase and

byte program freeing the system processor for other

tasks After receiving the erase setup and erase

confirm commands the state machine controls

block pre-conditioning and erase returning progress

via the Status Register Programming is similarly

controlled after destination address and expected

data are supplied The program algorithm of past In-

tel Flash Memories is now regulated by the state

machine including program pulse repetition where

required and internal verification and margining of

data

6

Data Protection

Depending on the application the system designer

may choose to make the VPP power supply switcha-

ble (available only when memory updates are re-

quired) or hardwired to VPPH When VPP e VPPL

memory contents cannot be altered The 28F001BX

Command Register architecture provides protection

from unwanted program or erase operations even

when high voltage is applied to VPP Additionally all

functions are disabled whenever VCC is below the

write lockout voltage VLKO or when RP is at VIL

The 28F001BX accommodates either design prac-

tice and encourages optimization of the processor-

memory interface

The two-step program erase write sequence to the

Command Register provides additional software

write protection

1FFFF

1E000

1DFFF

1D000

1CFFF

1C000

1BFFF

8-KByte BOOT BLOCK

4-KByte PARAMETER BLOCK

4-KByte PARAMETER BLOCK

112-KByte MAIN BLOCK

00000

Figure 7 28F001BX-T Memory Map

1FFFF

112-KByte MAIN BLOCK

04000

03FFF

03000

02FFF

02000

01FFF

4-KByte PARAMETER BLOCK

4-KByte PARAMETER BLOCK

8-KByte BOOT BLOCK

00000

Figure 8 28F001BX-B Memory Map

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