PRELIMINARY TECHNICAL DATA
ADM1486–SPECIFICATIONS (VCC = +5 V ± 5%. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
Min Typ Max
DRIVER
Differential Output Voltage, VOD
2.0
2.1
VOD3
2.1
⌬|VOD| for Complementary Output States
Common-Mode Output Voltage VOC
⌬|VOD| for Complementary Output States
Output Short Circuit Current(VOUT=High) 60
Output Short Circuit Current(VOUT=Low) 60
CMOS Input Logic Threshold Low, VINL
CMOS Input Logic Threshold High, VINH 2.0
Logic Input Current (DE, DI)
5.0
5.0
5.0
5.0
0.2
3
0.2
150
150
0.8
±1.0
RECEIVER
Differential Input Threshold Voltage, VTH –0.2
Input Voltage Hysteresis, ⌬VTH
70
Input Resistance
20
Input Current (A, B)
Logic Enable Input Current (RE)
CMOS Output Voltage Low, VOL
CMOS Output Voltage High, VOH
4.0
Short Circuit Output Current
7
Tristate Output Leakage Current
+0.2
+1
–0.8
±1
0.4
85
±1.0
POWER SUPPLY CURRENT
ICC (Outputs Enabled)
ICC (Outputs Disabled)
Specifications subject to change without notice.
1.2 2.0
0.9 1.5
Unit Test Conditions/Comments
V
R = Infinity, Figure 1
V
VCC = 5 V, R = 50 ⍀ (RS-422), Figure 1
V
R = 27 ⍀ (RS-485), Figure 1
V
VTST = –7 V to +12 V, Figure 2
V
R = 27 ⍀ or 50 ⍀, Figure 1
V
R = 27 ⍀ or 50 ⍀, Figure 1
V
R = 27 ⍀ or 50 ⍀
mA –7 V р VO р +12 V
mA –7 V р VO р +12 V
V
V
µA
V
–7 V р VCM р +12 V
m V VCM = 0 V
k⍀ –7 V р VCM р +12 V
m A VIN = 12 V
m A VIN = –7 V
µA
V
IOUT = +4.0 mA
V
IOUT = –4.0 mA
m A VOUT = GND or VCC
µ A 0.4 V р VOUT р +2.4 V
m A Outputs Unloaded, Digital Inputs = GND or VCC
m A Outputs Unloaded, Digital Inputs = GND or VCC
TIMING SPECIFICATIONS (VCC = +5 V ± 5%. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
Min Typ Max Unit Test Conditions/Comments
DRIVER
Propagation Delay Input to Output TPLH, TPHL
Driver O/P to O/P TSKEW
Driver Rise/Fall Time TR, TF
Driver Enable to Output Valid
Driver Disable Timing
48
0
5
8
8
15
ns
RL Diff = 54 ⍀ CL1 = CL2 = 100 pF, Figure 3
2
ns
RL Diff = 54 ⍀ CL1 = CL2 = 100 pF, Figure 3
10
ns
RL Diff = 54 ⍀ CL1 = CL2 = 100 pF, Figure 3
15 ns
15 ns
RECEIVER
Propagation Delay Input to Output TPLH, TPHL
8
12 20 ns CL = 15 pF, Figure 5
Skew |TPLH–TPHL|
0
2
ns
Receiver Enable TEN1
5
10 ns Figure 6
Receiver Disable TEN2
5
10 ns Figure 6
Specifications subject to change without notice.
–2–
REV. B