ADM1166
Parameter
Standard (Digital Output) Mode
(PDO1 to PDO10)
VOH
VOL
IOL2
ISINK2
RPULL-UP
ISOURCE (VPx)2
Min
Typ Max Unit
2.4
VPU − 0.3
0
16
20
V
4.5 V
V
0.50 V
20 mA
60 mA
29 kΩ
2
mA
Three-State Output Leakage
Current
Oscillator Frequency
90
DIGITAL INPUTS (VXx, A0, A1)
Input High Voltage, VIH
2.0
Input Low Voltage, VIL
Input High Current, IIH
−1
Input Low Current, IIL
Input Capacitance
Programmable Pull-Down Current,
IPULL-DOWN
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH
2.0
Input Low Voltage, VIL
Output Low Voltage, VOL2
SERIAL BUS TIMING3
Clock Frequency, fSCLK
Bus Free Time, tBUF
1.3
Start Setup Time, tSU;STA
0.6
Stop Setup Time, tSU;STO
0.6
Start Hold Time, tHD;STA
0.6
SCL Low Time, tLOW
1.3
SCL High Time, tHIGH
0.6
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Data Setup Time, tSU;DAT
100
Data Hold Time, tHD;DAT
250
Input Low Current, IIL
SEQUENCING ENGINE TIMING
State Change Time
10 μA
100 110 kHz
V
0.8 V
μA
1
μA
5
pF
20
μA
V
0.8 V
0.4 V
400 kHz
μs
μs
μs
μs
μs
μs
300 ns
300 ns
ns
ns
1
μA
10
μs
Test Conditions/Comments
VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA
VPU to VPx = 6.0 V, IOH = 0 mA
VPU ≤ 2.7 V, IOH = 0.5 mA
IOL = 20 mA
Maximum sink current per PDOx pin
Maximum total sink for all PDOx pins
Internal pull-up
Current load on any VPx pull-ups, that is, total source
current available through any number of PDO pull-up
switches configured onto any one VPx pin
VPDO = 14.4 V
All on-chip time delays derived from this clock
Maximum VIN = 5.5 V
Maximum VIN = 5.5 V
VIN = 5.5 V
VIN = 0 V
VDDCAP = 4.75 V, TA = 25°C, if known logic state is required
IOUT = −3.0 mA
VIN = 0 V
1 At least one of the VH and VPx pins must be ≥ 3.0 V to maintain the device supply on VDDCAP.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Guaranteed by design.
Rev. 0 | Page 6 of 32