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ADM1026JSTZ View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADM1026JSTZ Datasheet PDF : 56 Pages
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ADM1026
Parameter
Min Typ Max Test Conditions/Comments Unit
High Level Output Leakage Current, IOH
Output Low Voltage, VOL
PWM Output Frequency
0.1
1
VOUT = VCC
µA
0.4
IOUT = −3.0 mA, VCC = 3.3 V
V
75
Hz
DIGITAL OUTPUTS (INT, RESETMAIN, RESETBY)
Output Low Voltage, VOL
0.4
IOUT = −3.0 mA, VCC = 3.3 V
V
RESET Pulse Width
140 180 240
ms
OPEN DRAIN SERIAL DATABUS OUTPUT (SDA)
Output Low Voltage, VOL
0.4
IOUT = –3.0 mA, VCC = 3.3 V
V
High Level Output Leakage Current, IOH
0.1
1
VOUT = VCC
µA
SERIAL BUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH
2.2
V
Input Low Voltage, VIL
Hysteresis
0.8
V
500
mV
DIGITAL INPUT LOGIC LEVELS (ADD, CI, FAN 0 to 7, GPIO 0 to 16)7, 8
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis (Fan 0 to 7)
2.4
VCC = 3.3 V
V
0.8
VCC = 3.3 V
V
250
VCC = 3.3 V
mV
RESETMAIN, RESETSTBY
RESETMAIN Threshold
2.89 2.94 2.97 Falling voltage
V
RESETSBY Threshold
3.01 3.05 3.10 Falling voltage
V
RESETMAIN Hysteresis
60
mV
RESETSTBY Hysteresis
70
mV
DIGITAL INPUT CURRENT
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
–1
VIN = VCC
µA
1
VIN = 0
µA
20
pF
EEPROM RELIABILITY
Endurance9
100 700
kcycles
Data Retention10
10
Years
SERIAL BUS TIMING
See Figure 2 for all parameters.
Clock Frequency, fSCLK
400
kHz
Glitch Immunity, tSW
50
ns
Bus Free Time, tBUF
4.7
µs
Start Setup Time, tSU; STA
Start Hold Time, tHD; STA
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tr
SCL, SDA Fall Time, tf
4.7
µs
4
µs
4.7
µs
4
µs
1000
ns
300
ns
Data Setup Time, tSU; DAT
250
ns
Data Hold Time, tHD; DAT
300
ns
1 All voltages are measured with respect to GND, unless otherwise specified.
2 Typicals are at TA = 25°C and represent the most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V.
3 Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge.
4 Total unadjusted error (TUE) includes offset, gain, and linearity errors of the ADC, multiplexer, and on-chip input attenuators. VBAT is accurate only for VBAT voltages
greater than 1.5 V (see Figure 15).
5 Total analog monitoring cycle time is nominally 273 ms, made up of 18 ms × 11.38 ms measurements on analog input and internal temperature channels, and
2 ms × 34.13 ms measurements on external temperature channels.
6 The total fan count is based on two pulses per revolution of the fan tachometer output. The total fan monitoring time depends on the number of fans connected and
the fan speed. See the Fan Speed Measurement section for more details.
7 ADD is a three-state input that may be pulled high, low, or left open-circuit.
8 Logic inputs accept input high voltages up to 5 V even when device is operating at supply voltages below 5 V.
9 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117, and measured at −40°C, +25°C, and +85°C. Typical endurance at +25°C is 700,000 cycles.
10 Retention lifetime equivalent at junction temperature (TJ ) = 55°C as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6 V
derates with junction temperature as shown in Figure 16.
Rev. A | Page 4 of 56
 

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