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ADF4360-3BCP View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADF4360-3BCP
ADI
Analog Devices ADI
ADF4360-3BCP Datasheet PDF : 17 Pages
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ADF4360
PRELIMINARY TECHNICAL DATA
R COUNTER
The 14-bit R counter allows the input reference frequency
to be divided down to produce the reference clock to the
phase frequency detector (PFD). Division ratios from 1 to
16,383 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter
(N=BP+A) and produces an output proportional to the
phase and frequency difference between them. Figure 5 is a
simplified schematic. The PFD includes a programmable
delay element which controls the width of the anti-backlash
pulse. This pulse ensures that there is no deadzone in the
PFD transfer function and minimizes phase noise and
reference spurs. Two bits in the R Counter Latch, ABP2
and ABP1 control the width of the pulse. See Table 3.
HI
R DIVIDER
UP
D1
Q1
U1
CLR1
VP
CHARGE
PUMP
With LDP set to "1", five consecutive cycles of less than
15ns are required to set the lock detect. It will stay set
high until a phase error of greater than 25ns is detected on
any subsequent PD cycle.
The N-channel open-drain analog lock detect should be
operated with an external pull-up resistor of 10k
nominal. When lock has been detected this output will be
high with narrow low-going pulses .
DVDD
Analog Lock Detect
Digital Lock Detect
R Counter Output
N Counter Output
SDOUT
MUX
CONTROL
MUXOUT
U3
CP
DGND
ABP2
ABP1
HI
N DIVIDER
CLR2
D2
Q2
DOWN
U2
CPGND
R DIVIDER
N DIVIDER
CP OUTPUT
Figure 5. PFD Simplified Schematic and Timing (In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4360 family allows
the user to access various internal points on the chip. The
state of MUXOUT is controlled by M3, M2 and M1 in
the Function Latch. Table 5 shows the full truth table.
Figure 6 shows the MUXOUT section in block diagram
form.
Lock Detect
MUXOUT can be programmed for two types of lock
detect: digital lock detect and analog lock detect
Digital lock detect is active high. When LDP in the R
Counter latch is set to 0, digital lock detect is set high
when the phase error on three consecutive Phase Detector
cycles is less than 15ns.
Figure 6. MUXOUT Circuit
INPUT SHIFT REGISTER
The ADF4360 familys digital section includes a 24-bit
input shift register, a 14-bit R counter and a 19-bit N
counter, comprising a 5-bit A counter and a 13-bit B
counter. Data is clocked into the 24-bit shift register on
each rising edge of CLK. The data is clocked in MSB
first. Data is transferred from the shift register to one of
four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits
(C2, C1) in the shift register. These are the two lsb's
DB1, DB0 as shown in the timing diagram of Figure 1.
The truth table for these bits is shown in Table 6. Table 1
shows a summary of how the latches are programmed.
Table I. C2, C1 Truth Table
Control Bits
C2
C1
Data Latch
0
0
Control Latch
0
1
R Counter
1
0
N Counter (A & B)
1
1
Test Modes Latch
8
REV. PrP 01/03
 

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