ADF4159CCPZ-RL7 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADF4159CCPZ-RL7
Analog Devices
ADF4159CCPZ-RL7 Datasheet PDF : 36 Pages
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Data Sheet
DEVIATION REGISTER (R5) MAP
When Bits DB[2:0] are set to 101, the on-chip deviation register
(Register R5) is programmed (see Figure 30).
Reserved Bit
The reserved bit must be set to 0 for normal operation.
TXDATA Invert
When Bit DB30 is set to 0, events triggered by TXDATA occur
on the rising edge of the TXDATA pulse. When Bit DB30 is set
to 1, events triggered by TXDATA occur on the falling edge of
the TXDATA pulse.
TXDATA Ramp Clock
When Bit DB29 is set to 0, the clock divider clock is used to
clock the ramp. When Bit DB29 is set to 1, the TXDATA clock
is used to clock the ramp.
Parabolic Ramp
When Bit DB28 is set to 1, the parabolic ramp is enabled. When
Bit DB28 is set to 0, the parabolic ramp is disabled. For more
information, see the Parabolic (Nonlinear) Ramp Mode section.
ADF4159
Interrupt
Bits DB[27:26] determine which type of interrupt is used. This
feature is used for reading back the INT and FRAC value of a
ramp at a given moment in time (a rising edge on the TXDATA
pin triggers the interrupt). From the INT and FRAC bits, the
frequency can be obtained. After readback, the sweep can continue
or stop at the readback frequency. For more information, see the
Interrupt Modes and Frequency Readback section.
FSK Ramp Enable
When Bit DB25 is set to 1, the FSK ramp is enabled. When
Bit DB25 is set to 0, the FSK ramp is disabled.
Dual Ramp Enable
When Bit DB24 is set to 1, the second ramp is enabled. When
Bit DB24 is set to 0, the second ramp is disabled.
Deviation Select
When Bit DB23 is set to 0, the first deviation word is selected.
When Bit DB23 is set to 1, the second deviation word is selected.
4-Bit Deviation Offset Word
Bits DB[22:19] determine the deviation offset word. The devia-
tion offset word affects the deviation resolution.
16-Bit Deviation Word
Bits DB[18:3] determine the signed deviation word. The
deviation word defines the deviation step.
4-BIT DEVIATION
OFFSET WORD
16-BIT DEVIATION WORD
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 TR1 0 I2 I1 0 0 DS1 DO4 DO3 DO2 DO1 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(1) C2(0) C1(1)
0 TXDATA INVERT
0 DISABLED
1 ENABLED
0 DUAL RAMP
0 DISABLED
1 ENABLED
DS1 DEV SEL
0 DEV WORD 1
1 DEV WORD 2
TR1 TXDATA RAMP CLK
0 CLK DIV
1 TXDATA
0 FSK RAMP
0 DISABLED
1 ENABLED
0 PARABOLIC RAMP
0 DISABLED
1 ENABLED
I2 I1
00
01
10
11
INTERRUPT
INTERRUPT OFF
LOAD CHANNEL CONTINUE SWEEP
NOT USED
LOAD CHANNEL STOP SWEEP
DO4 DO3 DO2 DO1
0000
0001
0010
.
.
.
.
.
.
.
.
0
1
11
1
00 0
1
00 1
DEV OFFSET WORD
0
1
2
.
.
7
8
9
D16 D15
0
1
.
.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
.
.
1
0
Figure 30. Deviation Register (R5) Map
... D2 D1
... 1 1
... .
.
... 1 1
... 1 0
... 0 1
... 0 0
... 1 1
... 1 0
... 0 1
... .
.
... 0 0
DEVIATION WORD
32,767
.
3
2
1
0
–1
–2
–3
.
–32,768
Rev. B | Page 21 of 36
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