ADF4159CCPZ-RL7 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADF4159CCPZ-RL7

Direct Modulation/Fast Waveform Generating, 13 GHz, Fractional-N Frequency Synthesizer

Analog Devices 

ADF4159

THEORY OF OPERATION

REFERENCE INPUT SECTION

Figure 18 shows the reference input stage. The SW1 and SW2

switches are normally closed (NC in Figure 18). The SW3 switch

is normally open (NO in Figure 18). When power-down is

initiated, SW3 is closed, and SW1 and SW2 are opened. In this

way, no loading of the REFIN pin occurs during power-down.

POWER-DOWN

CONTROL

NC 100kΩ

REFIN NC

SW2

SW1

SW3

NO

TO R COUNTER

BUFFER

Figure 18. Reference Input Stage

RF INPUT STAGE

Figure 19 shows the RF input stage. The input stage is followed

by a two-stage limiting amplifier to generate the current-mode

logic (CML) clock levels required for the prescaler.

BIAS

GENERATOR

1.6V

2kΩ

2kΩ

AVDD

RFINA

RFINB

Figure 19. RF Input Stage

AGND

RF INT DIVIDER

The RF INT CMOS divider allows a division ratio in the PLL

feedback counter. Division ratios from 23 to 4095 are allowed.

RF INT DIVIDER

FROM RF

INPUT STAGE

N COUNTER

N = INT + FRAC/MOD

TO PFD

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

INT

VALUE

MOD

VALUE

FRAC

VALUE

Figure 20. RF INT Divider

Data Sheet

25-BIT FIXED MODULUS

The ADF4159 has a 25-bit fixed modulus. This modulus allows

output frequencies to be spaced with a resolution of

fRES = fPFD/225

(1)

where fPFD is the frequency of the phase frequency detector

(PFD). For example, with a PFD frequency of 100 MHz,

frequency steps of 2.98 Hz are possible.

INT, FRAC, AND R COUNTER RELATIONSHIP

The INT and FRAC values, in conjunction with the R counter,

make it possible to generate output frequencies that are spaced

by fractions of the PFD frequency.

The RF VCO frequency (RFOUT) equation is

RFOUT = (INT + (FRAC/225)) × fPFD

(2)

where:

RFOUT is the output frequency of the external voltage

controlled oscillator (VCO).

INT is the preset divide ratio of the binary 12-bit counter

(23 to 4095).

FRAC is the numerator of the fractional division (0 to (225 − 1)).

The PFD frequency (fPFD) equation is

fPFD = REFIN × [(1 + D)/(R × (1 + T))]

(3)

where:

REFIN is the reference input frequency.

D is the REFIN doubler bit (0 or 1).

R is the preset divide ratio of the binary 5-bit programmable

reference (R) counter (1 to 32).

T is the REFIN divide-by-2 bit (0 or 1).

R COUNTER

The 5-bit R counter allows the input reference frequency (REFIN)

to be divided down to supply the reference clock to the PFD.

Division ratios from 1 to 32 are allowed.

Rev. B | Page 10 of 36

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