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ADF4158 View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADF4158 Datasheet PDF : 36 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADF4158
Parameter
NOISE CHARACTERISTICS
Normalized Phase Noise Floor4
Phase Noise Performance5
5805 MHz Output6
C Version1
Min
Typ Max Unit
Test Conditions/Comments
−213
−93
dBc/Hz
dBc/Hz
@ VCO output
@ 5 kHz offset, 32 MHz PFD frequency
1 Operating temperature for C version: −40°C to +125°C.
2 AC-coupling ensures AVDD/2 bias.
3 Guaranteed by design. Sample tested to ensure compliance.
4 This figure can be used to calculate phase noise for any application. Use the formula –213 + 10 log(fPFD) + 20 logN to calculate in-band phase noise performance as
seen at the VCO output.
5 The phase noise is measured with the EVAL-ADF4158EB1Z and the Agilent E5052A phase noise system.
6 fREFIN = 128 MHz; fPFD = 32 MHz; offset frequency = 5 kHz; RFOUT = 5805 MHz; INT = 181; FRAC = 13631488; loop bandwidth = 100 kHz.
TIMING SPECIFICATIONS
AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = SDGND = 0 V; TA = TMIN to TMAX, dBm referred to 50 Ω,
unless otherwise noted.
Table 2. Write Timing
Parameter
Limit at TMIN to TMAX (C Version)
t1
20
t2
10
t3
10
t4
25
t5
25
t6
10
t7
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
Write Timing Diagram
CLK
DATA
DB31 (MSB)
LE
t1
LE
t4
t5
t2
t3
DB30
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
Figure 2. Write Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t7
t6
Rev. 0 | Page 4 of 36
 

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