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ADF4154BCP View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADF4154BCP
ADI
Analog Devices ADI
ADF4154BCP Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADF4154
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Pin Function Descriptions...................... 6
Typical Performance Characteristics ............................................. 7
Circuit Description........................................................................... 9
Reference Input Section............................................................... 9
RF Input Stage............................................................................... 9
RF INT Divider............................................................................. 9
INT, FRAC, MOD, and R Relationship ..................................... 9
R-Counter ...................................................................................... 9
Phase Frequency Detector (PFD) and Charge Pump.............. 9
MUXOUT and Lock Detect...................................................... 10
Input Shift Registers ................................................................... 10
Program Modes .......................................................................... 10
Registers ........................................................................................... 11
REVISION HISTORY
8/12—Rev. B to Rev. C
Changes to Figure 4 .......................................................................... 6
Updated Outline Dimensions (Changed CP-20-1 to CP-20-6) .... 22
Changes to Ordering Guide .......................................................... 22
9/11—Rev. A to Rev. B
Changes to Noise Characteristics Parameter ................................ 3
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22
12/06—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Changes to Applications .................................................................. 1
Changes to Functional Block Diagram.......................................... 1
Changes to Specifications ................................................................ 3
Changes to Absolute Maximum Ratings ....................................... 5
Changes to Typical Performance Characteristics Conditions .... 7
Replaced Figure 5 through Figure 7............................................... 7
Data Sheet
Register Definitions ................................................................... 16
R-Divider Register, R1 ............................................................... 16
Control Register, R2 ................................................................... 16
Noise and Spur Register, R3 ...................................................... 17
Reserved Bits............................................................................... 17
Initialization Sequence .............................................................. 18
RF Synthesizer: A Worked Example ........................................ 18
Modulus....................................................................................... 18
Reference Doubler and Reference Divider ............................. 18
12-Bit Programmable Modulus ................................................ 18
Spurious Optimization and Fast Lock..................................... 18
Fast-Lock Timer and Register Sequences ............................... 19
Fast Lock: An Example .............................................................. 19
Fast Lock: Loop Filter Topology............................................... 19
Spur Mechanisms ....................................................................... 19
Spur Consistency........................................................................ 20
Filter Design—ADIsimPLL....................................................... 20
Interfacing ................................................................................... 20
PCB Design Guidelines for Chip Scale Package .................... 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
Changes to Figure 13.........................................................................8
Changes to R-Divider Register Map ............................................ 13
Changes to Control Register Map ................................................ 14
Change to REFIN Doubler Section................................................ 18
Added Initialization Sequence Section........................................ 18
Change to 12-Bit Programmable Modulus Section ................... 18
Changes to Fast-Lock Timer and Register Sequences Section........19
Changes to Fast Lock: Loop Filter Topology Section ................ 19
Deleted Spurious Signal Section................................................... 18
Added Spur Mechanisms Section ................................................ 19
Added Spur Consistency Section ................................................. 20
Change to Filter Design—ADIsimPLL Section.......................... 20
Change to Interfacing Section ...................................................... 20
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22
5/04—Revision 0: Initial Version
Rev. C | Page 2 of 24
 

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