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ADF4153BRU-REEL7 View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADF4153BRU-REEL7
ADI
Analog Devices ADI
ADF4153BRU-REEL7 Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADF4153
RSET 1
CP 2
CPGND 3
AGND 4
RFINB 5
RFINA 6
AVDD 7
REFIN 8
16 VP
15 DVDD
14 MUXOUT
ADF4153
TOP VIEW
(Not to Scale)
13 LE
12 DATA
11 CLK
10 SDVDD
9 DGND
Figure 3. TSSOP Pin Configuration
CPGND 1
AGND 2
AGND 3
RFINB 4
RFINA 5
PIN 1
INDICATOR
ADF4153
TOP VIEW
(Not to Scale)
15 MUXOUT
14 LE
13 DATA
12 CLK
11 SDVDD
NOTES
1. THE LFCSP HAS AN EXPOSED PADDLE
THAT MUST BE CONNECTED TO GND.
Figure 4. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Pin No.
TSSOP LFCSP Mnemonic Description
1
19
RSET
Connecting a resistor between RSET and ground sets the maximum charge pump output current.
The relationship between ICP and RSET is
I CPMAX
=
25.5
RSET
where RSET = 5.1 kΩ and ICPMAX = 5 mA.
2
20
CP
Charge Pump Output. When enabled, CP provides ±ICP to the external loop filter, which in turn
drives the external VCO.
3
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
4
2, 3
AGND
Analog Ground. This is the ground return path of the prescaler.
5
4
RFINB
Complementary Input to the RF Prescaler. This pin should be decoupled to the ground plane
with a small bypass capacitor, typically 100 pF (see Figure 12).
6
5
RFINA
Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
7
6, 7
AVDD
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. AVDD has a value of 3 V ± 10%. AVDD must have the same
voltage as DVDD.
8
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input
resistance of 100 kΩ (see Figure 11). This input can be driven from a TTL or CMOS crystal oscillator,
or it can be ac-coupled.
9
9, 10
DGND
Digital Ground.
10
11
SDVDD
Σ-Δ Power. Decoupling capacitors to the digital ground plane should be placed as close as possible
to this pin. SDVDD has a value of 3 V ± 10%. SDVDD must have the same voltage as DVDD.
11
12
CLK
Serial Clock Input. The serial clock is used to clock in the serial data to the registers. The data is
latched into the shift register on the CLK rising edge. This input is a high impedance CMOS input.
12
13
DATA
Serial Data Input. The serial data is loaded MSB first; the two LSBs are the control bits. This input is
a high impedance CMOS input.
13
14
LE
Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one
of four latches; the latch is selected using the control bits.
14
15
MUXOUT
This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled reference
frequency to be externally accessed.
15
16, 17
DVDD
Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DVDD has a value of 3 V ± 10%. DVDD must have
the same voltage as AVDD.
16
18
VP
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
Rev. D | Page 7 of 24
 

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