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ADF4153WYRUZ-R7 View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADF4153WYRUZ-R7
ADI
Analog Devices ADI
ADF4153WYRUZ-R7 Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADF4153
Parameter
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
(PNSYNTH) 5
Normalized 1/f Noise (PN1_f)6
Phase Noise Performance7
1750 MHz Output8
B Version1 Y Version2 Unit
−220
−114
−220
−114
dBc/Hz typ
dBc/Hz typ
−102
−102
dBc/Hz typ
Test Conditions/Comments
PLL loop BW = 500 kHz
Measured at 10 kHz offset, normalized to 1 GHz
@ VCO output
@ 5 kHz offset, 25 MHz PFD frequency
1 Operating temperature for B version is −40°C to +85°C.
2 Operating temperature for Y version is −40°C to +125°C.
3 AC coupling ensures AVDD/2 bias.
4 Guaranteed by design. Sample tested to ensure compliance.
5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(FPFD). PNSYNTH = PNTOT − 10 log(FPFD) − 20 log(N).
6 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF,
and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
7 The phase noise is measured with the EVAL-ADF4153EBZ1 and the Agilent E5500 phase noise system.
8 fREFIN = 100 MHz; FPFD = 25 MHz; offset frequency = 5 kHz; RFOUT = 1750 MHz; N = 70; loop BW = 20 kHz; lowest noise mode.
TIMING SPECIFICATIONS
AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted;
dBm referred to 50 Ω.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit at TMIN to TMAX (B Version)
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
CLK
t4
t5
DATA
DB23 (MSB)
LE
t1
LE
t2
t3
DB22
DB2
DB1
(CONTROL BIT C2)
Figure 2. Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t7
t6
Rev. D | Page 5 of 24
 

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