ADF4107BRU-REEL7 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADF4107BRU-REEL7 Datasheet PDF : 20 Pages
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ADF4107
Data Sheet
Parameter
Phase Noise Performance12
900 MHz Output13
6400 MHz Output14
6400 MHz Output15
Spurious Signals
900 MHz Output13
6400 MHz Output14
6400 MHz Output15
B Version1 B Chips2 (Typ) Unit
−93
−93
−76
−76
−83
−83
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
−90/−92
−65/−70
−70/−75
−90/−92
−65/−70
−70/−75
dBc typ
dBc typ
dBc typ
Test Conditions/Comments
@ VCO output
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 1 MHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD
frequency
@ 200 kHz/400 kHz and 200 kHz PFD
frequency
@ 1 MHz/2 MHz and 1 MHz PFD frequency
1 Operating temperature range (B version) is −40°C to +85°C.
2 The B chip specifications are given as typical values.
3 Use a square wave for lower frequencies, below the minimum stated.
4 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
5 AVDD = DVDD = 3 V.
6 AC-coupling ensures AVDD/2 bias.
7 Guaranteed by design. Sample tested to ensure compliance.
8 TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 7.0 GHz.
9 TA = 25°C; AVDD = DVDD = 3.3 V; R = 16,383; A = 63; B = 891; P = 32; RFIN = 7.0 GHz.
10 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value)
and 10 log(FPFD). PNSYNTH = PNTOT – 20 logN −10 logFPFD.
11 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF,
and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in
ADIsimPLL.
12 The phase noise is measured with the EV-ADF411xSD1Z evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the
synthesizer (fREFOUT = 10 MHz @ 0 dBm).
13 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop BW = 20 kHz.
14 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 6400 MHz; N = 32,000; loop BW = 20 kHz.
15 fREFIN = 10 MHz; fPFD = 1 MHz; offset frequency = 1 kHz; fRF = 6400 MHz; N = 6400; loop BW = 100 kHz.
TIMING CHARACTERISTICS
AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN,
unless otherwise noted. 1
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
Limit2 (B Version)
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
DATA to CLOCK setup time
DATA to CLOCK hold time
CLOCK high duration
CLOCK low duration
CLOCK to LE setup time
LE pulse width
1 Guaranteed by design but not production tested.
2 Operating temperature range (B Version) is −40°C to +85°C.
t3
t4
CLOCK
DATA DB23 (MSB)
t1
t2
DB22
LE
LE
DB2
DB1 (CONTROL
BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t6
t5
Figure 2. Timing Diagram
Rev. D | Page 4 of 20
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