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ADCMP562BRQ View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADCMP562BRQ
ADI
Analog Devices ADI
ADCMP562BRQ Datasheet PDF : 16 Pages
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Dual High Speed PECL Comparators
ADCMP561/ADCMP562
FEATURES
Differential PECL compatible outputs
700 ps propagation delay input to output
75 ps propagation delay dispersion
Input common-mode range: –2.0 V to +3.0 V
Robust input protection
Differential latch control
Internal latch pull-up resistors
Power supply rejection greater than 85 dB
700 ps minimum pulse width
1.5 GHz equivalent input rise time bandwidth
Typical output rise/fall time of 500 ps
ESD protection > 4kV HBM, >200V MM
Programmable hysteresis
APPLICATIONS
Automatic test equipment
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Disk drive read channel detection
Hand-held test instruments
Zero-crossing detectors
Line receivers and signal restoration
Clock drivers
GENERAL DESCRIPTION
The ADCMP561/ADCMP562 are high speed comparators
fabricated on Analog Devices’ proprietary XFCB process. The
devices feature a 700 ps propagation delay with less than 75 ps
overdrive dispersion. Dispersion, a measure of the difference in
propagation delay under differing overdrive conditions, is a
particularly important characteristic of comparators. A separate
programmable hysteresis pin is available on the ADCMP562.
A differential input stage permits consistent propagation delay
with a wide variety of signals in the common-mode range from
−2.0 V to +3.0 V. Outputs are complementary digital signals that
FUNCTIONAL BLOCK DIAGRAM
HYS*
NONINVERTING
INPUT
INVERTING
INPUT
ADCMP561/
ADCMP562
Q OUTPUT
Q OUTPUT
LATCH ENABLE
INPUT
LATCH ENABLE
INPUT
*ADCMP562 ONLY
Figure 1.
QA 1
16 QB
QA 2
15 QB
VDD 3
LEA 4
LEA 5
ADCMP561
TOP VIEW
(Not to Scale)
14 GND
13 LEB
12 LEB
VEE 6
–INA 7
11 VCC
10 –INB
+INA 8
9 +INB
VDD 1
20 VDD
QA 2
19 QB
QA 3
VDD 4
LEA 5
LEA 6
18 QB
ADCMP562 17 GND
TOP VIEW
(Not to Scale)
16 LEB
15 LEB
VEE 7
14 VCC
–INA 8
13 –INB
+INA 9
12 +INB
HYSA 10
11 HYSB
Figure 2. ADCMP561 16-Lead QSOP Figure 3. ADCMP562 20-Lead QSOP
are fully compatible with PECL 10 K and 10 KH logic families.
The outputs provide sufficient drive current to directly drive
transmission lines terminated in 50 Ω to VDD − 2 V. A latch
input, which is included, permits tracking, track-and-hold, or
sample-and-hold modes of operation. The latch input pins
contain internal pull-ups that set the latch in tracking mode
when left open.
The ADCMP561/ADCMP562 are specified over the industrial
temperature range (−40°C to +85°C).
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
 

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