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ADC912A View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADC912A Datasheet PDF : 16 Pages
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ADC912A
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic Description
l
2
3
4 . . . 11
13 . . . 16
AIN
VREFIN
AGND
D11 . . . D4
D3/11 . . . D0/8
Analog Input. 0 V to 10 V.
Voltage Reference Input. Requires external –5 V reference.
Analog Ground.
Three-state data outputs become active when CS and RD are brought low.
Individual pin function is dependent upon High Byte Enable (HBEN) input.
DATA BUS OUTPUT, CS and RD = LOW
Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 14 Pin 15 Pin 16
Mnemonic*
HBEN = LOW
D11
DB11
D10
DB10
D9
DB9
D8
DB8
D7
DB7
D6
DB6
D5
DB5
D4
DB4
D3/11
DB3
D2/10
DB2
D1/9
DB1
D0/8
DB0
HBEN = HIGH DB11 DB10 DB9 DB8 Low Low Low Low DB11 DB10 DB9 DB8
*D11 . . . D0/8 are the ADC data output pins.
DB11 . . . DB0 are the 12-bit conversion results. DB11 is the MSB.
12
DGND
Digital Ground.
17
CLK IN
Clock Input Pin. An external TTL-compatible clock may be applied to this pin. Alternatively a crystal or
ceramic resonator may be connected between CLK IN (Pin 17) and CLK OUT (Pin 18).
18
CLK OUT Clock Output Pin. An inverted CLK IN signal appears at CLK OUT when an external clock is used. See
CLK IN (Pin 17) description for crystal (resonator).
19
HBEN
High Byte Enable Input. Its primary function is to multiplex the 12 bits of conversion data onto the lower
D7 . . . D0/8 outputs (4 MSBs or 8 LSBs). See pin description 4 . . . 11 and 13 . . . 16. Also disables
conversion start when HBEN is high.
20
RD
READ Input. This active LOW signal, in conjunction with CS, is used to enable the output data three
state drivers and initiates a conversion if CS and HBEN are low.
21
CS
Chip Select Input. This active LOW signal, in conjunction with RD, is used to enable the output data
three-state drivers and initiates a conversion if RD and HBEN are low.
22
BUSY
BUSY output indicates converter status. BUSY is LOW during conversion.
23
VSS
24
VDD
Negative Supply, –12 V or –15 V.
Positive Supply, +5 V.
PIN CONFIGURATION
AIN 1
VREFIN 2
AGND 3
24 VDD
23 VSS
22 BUSY
D11 4
21 CS
D10 5 ADC912A 20 RD
D9 6 TOP VIEW 19 HBEN
(Not to Scale)
D8 7
18 CLK OUT
D7 8
17 CLK IN
D6 9
D5 10
D4 11
16 D0/8
15 D1/9
14 D2/10
DGND 12
13 D3/11
0V TO 10V
ANALOG INPUT
5V
REFERENCE
SOURCE C1
1 AIN
VDD 24
C2 2 VREFIN
+ 3 AGND
VSS 23
BUSY 22
4 D11
CS 21
5 D10 ADC912A RD 20
6 D9
HBEN 19
7 D8
CLK OUT 18
8 D7
9 D6
10 D5
11 D4
CLK IN 17
D0/8 16
D1/9 15
D2/10 14
12 DGND
D3/11 13
8-BIT OR 16-BIT P DATA BUS
+5V
12V TO 15V
STATUS
OUTPUT
P
CONTROL
INPUTS
C3
XTAL
C4
XTAL = 1MHz, C1 = 0.1 F, C3 = 10 F
C3, C4 = 30pF TO 100pF DEPENDING ON XTAL CHOSEN
Figure 10. Basic Connection Diagram
–6–
REV. B
 

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