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ADC912AFP View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADC912AFP Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADC912A–SPECIFICATIONS (VDD = +5 V ؎ 5%, VSS = –11.4 V to –15.75 V, VREFIN = –5 V, Analog Input O V to
10 V; External fCLK = 1.25 MHz; –40؇C to +85؇C applies to ADC912A/F unless otherwise noted.)
Parameter
Symbol Conditions
Min Typ
Max Unit
STATIC ACCURACY
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Full-Scale Tempco1
INL
DNL
VZSE
GFSE
TCGFS
VDD = +5 V, VSS = –12 V
VDD = +5 V, VSS = –12 V
–1
–1
–5
–6
5
ANALOG INPUT
Input Voltage Range
VIN
0
Input Current Range
IIN
0
POWER SUPPLIES
Positive Supply Current
IDD
VDD = +5 V2
5
Negative Supply Current
ISS
VSS = –12 V2
3
Power Consumption
PDISS
VDD = +5 V2, VSS = –12 V2
70
Power Supply Rejection Ratio PSRR+ VDD = ± 5%, AIN = 10 V
1/2
PSRR–
VSS = ± 5%, AIN = 10 V
1/2
DIGITAL INPUTS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Digital Input Capacitance
VINH
VINL
IIN
CIN
CS, RD, HBEN
2.4
CS, RD, HBEN
CS, RD, HBEN
Digital Inputs, CS, RD, HBEN, CLKIN
7
DIGITAL OUTPUTS
Logic Input High Voltage
Logic Input Low Voltage
Three-State Output Leakage
Digital Input Capacitance
VOH
VOL
IOZ
COUT
ISOURCE = 0.2 mA
ISINK = 1.6 mA
D11–D0/8
D11–D0/81
4
8
DYNAMIC PERFORMANCE
Conversion Time
TC
fCLK = 1.25 MHz3
Synchronous Clock
Asynchronous Clock
10.4
+1
LSB
+1
LSB
+5
LSB
+6
LSB
15
ppm/°C
10
V
3
mA
7
mA
5
mA
95
mW
4
LSB
4
LSB
V
0.8 V
±1
µA
10
pF
V
0.4 V
10
µA
15
pF
10.4 µs
11.2 µs
NOTES
1Guaranteed by design.
2Converter inactive; CS, RD = High, AIN = 10 V.
3See Synchronizing Start Conversion information in Converter Operation Details. Typicals (typ) are median values measured at 25 °C. See Typical Performance
Characteristics for additional information.
Specifications subject to change without notice.
DBN
3k
CL
DGND
A. HIGH-Z TO V OH (t3)
AND VOL TO VOH (t6)
5V
DBN
3k
CL
DGND
B. HIGH-Z TO VOL (t3)
AND V OH TO VOL (t6)
Figure 3. Load Circuits for Access Time
5V
DBN
3k
DGND
10pF
DBN
3k
10pF
DGND
A. VOH TO HIGH-Z
B. VOL TO HIGH-Z
Figure 4. Load Circuits for Output Float Delay
–2–
REV. B
 

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