Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits
Номер в каталоге  

ADC1031 Просмотр технического описания (PDF) - National ->Texas Instruments

Номер в каталогеADC1031 National-Semiconductor
National ->Texas Instruments National-Semiconductor
Компоненты Описание10-Bit Serial I/O A/D Converters with Analog Multiplexer and Track/Hold Function
ADC1031 Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Electrical Characteristics (Continued)
The following specifications apply for VCC e a5 0V VREF e a4 6V fS e 700 kHz and fC e 3 MHz unless otherwise
specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C
Symbol
Parameter
Conditions
Typical Limit
(Note 8) (Note 9)
Units
(Limits)
DIGITAL AND DC CHARACTERISTICS
VIN(1)
VIN(0)
IIN(1)
IIN(0)
VOUT(1)
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
Logical ‘‘1’’ Output Voltage
VOUT(0) Logical ‘‘0’’ Output Voltage
IOUT
TRI-STATE Output Current
ISOURCE Output Source Current
ISINK Output Sink Current
ICC
Supply Current
AC CHARACTERISTICS
VCC e 5 25 VDC
VCC e 4 75 VDC
VIN e 5 0 VDC
VIN e 0 VDC
VCC e 4 75 VDC
IOUT e b360 mA
IOUT e b10 mA
VCC e 4 75 VDC
IOUT e 1 6 mA
VOUT e 0V
VOUT e 5V
VOUT e 0V
VOUT e VCC
CS e HIGH VREF Open
0 005
b0 005
20
08
25
b2 5
V (min)
V (max)
mA (max)
mA (max)
b0 01
0 01
b14
16
15
24
45
04
b3
3
b6 5
80
3
V (min)
V (min)
V (max)
mA (max)
mA (max)
mA (min)
mA (min)
mA (max)
fC
Conversion Clock (CCLK)
Frequency
07
MHz (min)
40
3 0 MHz (max)
fS
Serial Data Clock (SCLK)
Frequency (Note 13)
TC
Conversion Time
fC e 3 MHz R L e ‘‘0’’
fC e 3 MHz R L e ‘‘1’’
fC e 3 MHz R L e ‘‘0’’ or R L e ‘‘1’’
Not Including MUX Addressing and
Analog Input Sampling Times
183
kHz (min)
622
kHz (min)
2
1 0 MHz (max)
41 (1 fC) (max)
a 200 ns
tCA
Analog Sampling Time
After Address is Latched CS e Low
4 5 (1 fS) (max)
a 200 ns
tACC
Access Time Delay from CS or OE
Falling Edge to DO Data Valid
OE e ‘‘0’’
100
200
ns (max)
tSET-UP
t1H t0H
Set-up Time of CS Falling
Edge to SCLK Rising Edge
Delay from OE or CS Rising
Edge to DO TRI-STATE
RL e 3 kX CL e 100 pF
75
150
ns (min)
100
120
ns (max)
tHDI
DI Hold Time from SCLK Rising Edge
tSDI
DI Set-up Time to SCLK Rising Edge
0
50
ns (min)
50
100
ns (min)
3
Direct download click here

 

Share Link : 
All Rights Reserved© datasheetq.com 2015 - 2019  ] [ Privacy Policy ] [ Request Datasheet  ] [ Contact Us ]