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ADC08831 Просмотр технического описания (PDF) - National ->Texas Instruments

Номер в каталогеADC08831 National-Semiconductor
National ->Texas Instruments National-Semiconductor
Компоненты Описание8-Bit Serial I/O CMOS A/D Converters with Multiplexer and Sample/Hold Function
ADC08831 Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Electrical Characteristics (Continued)
The following
apply for TA
=spTeJci=ficTaMtioINnstoapTpMlAyXf;oralVl CoCthe=r
VREF
limits
=TA+5=VTDJC,=a2n5d˚CfC.LK
=
2
MHz
unless
otherwise
specified.
Boldface
limits
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
DC CHARACTERISTICS
ICC
Supply Current ADC08831
CS = VCC
CLK = VCC
CS = LOW
0.6
1.0
mA (max)
1.7
2.4
mA (max)
ICC
Supply Current ADC08832
CS = VCC
CLK = VCC (Note 16)
CS = LOW
1.3
1.8
mA (max)
2.4
3.5
mA (max)
Electrical Characteristics
The following specifications apply for VCC = VREF = +5 VDC, and tr = tf = 20 ns unless otherwise specified. Boldface limits
apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
fCLK
Clock Frequency
Clock Duty Cycle
(Note 14)
2
MHz (max)
40
% (min)
60
% (max)
TC
Conversion Time (Not Including MUX
fCLK = 2MHz
Addressing Time)
8
1/fCLK (max)
4
µs (max)
tCA
tSET-UP
Acquisition Time
CS Falling Edge or Data Input
Valid to CLK Rising Edge
12
1/fCLK (max)
25
ns (min)
tHOLD
Data Input Valid after CLK
Rising Edge
20
ns (min)
tpd1, tpd0
CLK Falling Edge to Output
Data Valid (Note 15)
CL = 100 pF:
Data MSB First
Data LSB First
250
ns (max)
200
ns (max)
t1H, t0H
TRI-STATE Delay from Rising Edge
CL = 10 pF, RL = 10 k
50
ns
of CS to Data Output and SARS Hi-Z
(see TRI-STATE Test Circuits)
CIN
CIN
COUT
Capacitance of Analog Input (Note 17)
Capacitance of Logic Inputs
Capacitance of Logic Outputs
CL = 100 pF, RL = 2 k
180
ns (max)
13
pF
5
pF
5
pF
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